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Recent content by balajir

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    Calculate area Consumption of a module on an ASIC

    Hi., I need to know how to calculate the area consumed by a module., any module like for example a 5:1 MUX or a adder circuit on an ASIC built using 90nm Technology Like., i know till this level that., Area consumed by the circuit on chip is equal to (Area Consumed by 1 Logic gate x No. of...
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    help needed in verilog

    A bit more explanation of your requirement will be helpful in getting you the exact solution a quick google search of your requirement gave me this URL which i thought might be useful http://www.fpga4fun.com/PWM_DAC.html
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    A 8 Bit Shift Register in a Single Slice

    Hmmm... the site u showed does tht., the thing is., i can just take 1 bit out of the LUT at a time., fine yes thts 1 slice i agree., but i need to take 8 bits out of it @ a time., i mean take 8 bits @ a time., i have implemented a SRL16, which can do the job in 8 LUTS, i.e., in 4 slices...
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    I need Verilog Code for 8 bit shift register in 1 CLB

    Hi., I urgently require the verilog code for a 8 bit Shift Register in a single Slice., I can design normal shift registers, in 5 slices, but I want it in 1 or 2 CLBs, I Don't want code generated through IPCoreGen, i want the complete code., Please if someone can give me the code or can...
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    A 8 Bit Shift Register in a Single Slice

    Hi., I urgently require the verilog code for a 8 bit Shift Register in a single Slice., I can design normal shift registers, in 5 slices, but I want it in 1 or 2 CLBs, Please if someone can give me the code or can tell me how to optimize it atleast it will be great Thanks
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