Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by bala_EE

  1. B

    reg wire difference in combinational circuit...

    So, everytime we use a reg or wire, the only reason we are doing so, is that, those are the rules of verilog and there is no other reason or explanation behind it. Is that so?
  2. B

    reg wire difference in combinational circuit...

    Can you please tell me why we use reg and wire in one manner in testbenches and why is it used in the opposite manner in the instances?
  3. B

    reg wire difference in combinational circuit...

    Lets say you have clk as input in a test module. We have to put some logic which imitates a clock signal. Something like.... always $10 clk <= ~clk; How can we use clk as a wire, if clk is in the LHS and is in an always block? We have to use clk as reg.
  4. B

    reg wire difference in combinational circuit...

    Why do we do that? Why is it that testbenches have regs as inputs and instances have wires as inputs?
  5. B

    reg wire difference in combinational circuit...

    I too have the same question. I dont really understand the difference between them... Looking forward to understanding them in this post...
  6. B

    sdc constraints in detail

    Like I said the design constraints are mentioned by the library vendor. For example, if the library file contains three types of Wire Load Models namely small, medium and large. We can choose from the three and specify through the SDC file that we would like DC to use SMALL or MEDIUM or LARGE...
  7. B

    Question on delay insertion in DC synthesis

    Why do you want to use some other cell? If so what do you think is possible to use other than INV?
  8. B

    sdc constraints in detail

    Constraints in general can be divided into two categories, namely, Design Rule Constraints and Optimizations Constraints. Design rule constraints are implicitly defined by the vendor of the library that is being used for synthesizing the design. For example, transition time, fanout load and cap...
  9. B

    Writing to a flash memory location

    Guys, Can anybody tell me how to write to a particular location in the flash memory of a Coldfire board?
  10. B

    FFT - need some good material

    Can anybody guide me to some good material on understanding FFT, that conveys the concept in the simplest way? I am looking forward to design a 64 point FFT. Thanks in advance.
  11. B

    [SOLVED] Cadence LVS Net-list Ambiguities

    I dont understand one thing here. You say that its a 21 bit RCA. But you have a single bit input for A and B. How does that work? Shouldnt the inputs A and B be 21 bit inputs?
  12. B

    [SOLVED] Cadence LVS Net-list Ambiguities

    I dont understand what you mean here by symmetry and "A and B circuits being equivalent". Its possible that I misunderstood what you meant. Can you please be more descriptive?
  13. B

    [SOLVED] Cadence LVS Net-list Ambiguities

    After generating the extracted view, open the extracted view and in the run LVS dialog box click on errors. A new dialog box opens showing the errors encountered. For each error, you can see the nets highlighted in yellow in the extracted view. Check these highlighted nets in the layout and...

Part and Inventory Search

Top