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Thank you Klaus,
I think NCO definitely will do that.
My intention is not to design such a clock source. I just need some clock with configurable random noise for simulation of some circuit which requires such a clock source. That's why I wanted to keep it simple. The vsource in "prbs" type...
I am trying to generate a clock signal with random noise, but not using complicated VCO models in Cadence Spectre.
One possible way I think is to use the vsource in analogLib with "prbs" type, and specify the bit file with "...0101..." pattern. So that, I can put the noise for the pattern as...
ashil_na, I think the 50MHz 3db bandwith is a spec when the opamp is in closed loop configration. Otherwise, things would be really hard just as jimito13 suggested, even in 65nm process.
If so, many structures of opamp could be your candidates. As the opamp is for a buffer, a two stage...
Hello, guys!
Would you please to recommendate some gratudate schools in which it is worth pusuiting a PhD degree in IC design area in USA?
Thank you in advance.
Hi, erikl. Thank you for your reply.
Maybe I didn't describe my question clearly. I know that the estimate current is about 0.37mA. And I calculated the current as follows.
Vc=Vin*(1/sCs)/(Rs+1/sCs)=Vin/(sRsCs+1)=0.3sin(2*pi*50)t (assume sRsCs-->0)
and then use
Ic=Cs*(dVc/dt)
to get the...
Hello, everyone!
It is a samping path of a SH circuit as shown in the image, and the paramater is annoated on the scheme. 50MHz is the maximum frequency of the input singal.
What I want to know is how to decide the width of the wire when layout this circuit. Is it something just based on...
For low power. I don't think there is big stuff we can do at layout level. To minish the parasitic cap may give some improvment, but it's still trivial. So I think sechmatic should be modified if low power is taken into account.
For arranging the components. I think avoiding the crosstalk...
Hi DenisMark,
Sorry for the late reply! I read the material you give me these two days and tried to simulate my opamp fully followed the automation testbench given by the application note, but I haven't got it yet because of my poor skill in writing script. And I will try it later, some...
Hi DenisMark,
Here is the Bode plot of the AC simulation.
Fig 1
[url=http://obrazki.elektroda.pl/100_1260887033.jpg][/
And the testbench circuit is similar to Fig 2.
Fig 2
[url=http://obrazki.elektroda.pl/61_1260887720.jpg][/
As you can see, there is a terrace of the gain curve. I think it's...
Thanks DenisMark!
Yes it's fully differential amplifier, and the other 2 compensation you mentioned is at the right side of Fig 6 and is also omitted for simplify. I'm sorry for forgetting mentioning it in the post. So there are 4 compensate cap in the amplifier and each is 2.5pF.
the settling...
I want to design an OTA for SH circuit in Pipelined ADC and some of the important specicications are,
Vdd=1.2V
VCMI=VCMO=0.5V
Adc>96dB
GBW>400MHz
SR>300V/us
CL=Cc=5pF(for low-noise)
The two stage folded-cascode gain-boosting OTA with hybrid cascode compensation is chosen to meet the spec(the...
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