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erk, unfortunately that doesnt work either.
by doesnt work, i mean the synthesizer whines about it still.
I would love to ignore the warning, but i am implementing a lookup table using case, where there are 64 cases, 64 lines of warnings for just a single module.
another question is, when i...
verilog set wire to parameter
is there any way i can set values to wire from parameter value (in verilog)?
say in VHDL, i can easily use conv_std_logic_vector function.
I tried setting it right away, eg
parameter bla = 10;
wire [6:1] thewire;
assign thewire = bla+5;
that works, but...
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