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Thank you for your reply. Would you please explain it in detail?
I have three .sdf files: maxsdf.v, minsdf.v and typesdf.v.
I'm using typesdf.v, and in the modelsim6.2b, I use this command:
# vsim +notimingchecks -sdftyp /testbench/DUT0=E:/asic_top/bmc_core_post_simulation/type.sdf...
Hi ads-ee.
Thank you very much for the reply!
So, you mean the sdf like "(INTERCONNECT si_pad PIW_2/PAD (0.000::0.000))" is OK?
And the "# ** Warning: (vsim-SDF-3924)E:/BMC/asic_top/post_simulation/asic_top_type.sdf: Out of 2774423 SDF statements, 2774423 had null values." can be ignored?
But...
I saw a warning like "Out of 2774423 SDF statements, 2774423 had null values." Do it mean that the SDF annotation have some problems?
# ** Warning: (vsim-SDF-3924)E:/BMC/asic_top/post_simulation/asic_top_type.sdf: Out of 2774423 SDF statements, 2774423 had null values.
# ** Note: (vsim-3587)...
I use the "fork join" in my testbench, but I find that the modelsim execute the first part firstly, when all the N times are finished, the second part is then executed.
I think the fork join doesn't work in my code.
Can anybody tell me why? Thank you.
The following is my code:
....
fork...
How to flatten a design?
I find that my design takes a lot of Logic Elements. The design has several hierarchies, I think if the design is flattened when synthesis, the synthesizer and the fitter can get a better result.
But I don't want to rewrite my verilog file.
How to flatten a design in...
I'm going to make a PCB board with StratixIII and DDR3 SDRAM. Address and command signal lines should be ended with termination resistance. I wonder, are these resistance already placed on the SODIMM? So I don't need to place them on my PCB board.
Is there anything else that I should pay...
Cite from https://www.altera.com/literature/hb/max2/max2_mii51002.pdf.
I don't quite understand the "NOT gate push-back technique", you say "push an inversion (that is, a NOT gate) back though a register and implement it on that register's data input if it is necessary to implement the...
modelsim optimization
I have simulated the testbench with Optimization OFF.
Then, I turned on the Optimization and run the simulation again.
Optimization really speed up the simulation.
But I found that the simulation results are different.
The results with Optimization ON must be wrong.
Why...
not gate push back fpga
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back.
What does "NOT Gate Push-Back" mean?
Thank you.
But in the simulation, errors occur at 381200ps(near rst_n 1->0) and 885200ps(near rst_n 0->1). The error messages all say "$setup(....,.....,....)".
Why there is also such error message when reset is activated?
Thank you very much for your help!
So, the same problem also exist when the asynchronous reset is activated when close to the active slope of the clock?
So, it's not my design's problem. Is there anything I can do to avoid its happening?
Does this problem matters? Does that means any design with asynchronous reset is...
My design is implemented on MAX7256AE.
I use QuartusII to systhesis and fit the design. The Classic Timing Analythesis reports that the fmax of the clk can get 84.03MHz, and no error or warnings are
reported.
I take timing simulation in Modelsim-SE6.2b and encounter with this error...
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