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Recent content by azerm

  1. azerm

    Beginner's question on DFT

    It is better N to be in form of 2^k; so for example 512 is a good choise for your problem. t = 0:0.001:0.6; t=t[1:512]; x = sin(2*pi*50*t)+sin(2*pi*120*t); then t and thus x has only 512 sample;
  2. azerm

    What is clock uncertainity and why does it happen?

    clock uncertainity clock skew is mainly delay in clock arrival between different points due to different clock network from clock source to those points. clock uncertainty is variation in clock period for one point, regardless of other points.
  3. azerm

    The technology library contains power information ?

    what do you mean about add this to your testbench? common power estimation tools use simulation results, ex. VCD file to do power estimation.
  4. azerm

    questions about Delay Chain

    in major digital std cell libs, there is some delay cell like DLYxx. look into the std cell list.
  5. azerm

    Successful IC5141USR? on SUSE10.3!

    suse 10.3 or opensuse 10.3?
  6. azerm

    IC610: icfb.exe: ../../src/xcb_lock.c:77: _XGetXCBBuffer: As

    ic610 error badwindow try sues 10 professional. it is the best for eda tools. ;both x86 (very good) & x64 (with a little try).
  7. azerm

    Error when using "verilog +gui" command in Cadence ICFB

    icfb cadence Hi, You must install a verilog tool like verilog-xl or ncverilog separately. They comes with IUS package (prev. LDV package).
  8. azerm

    Difference between RTL and behavioral code

    RTL Vs Behavioral Behavioral codes may be synthesizable or non-synthesizable. If you want to use tools like behavioral compiler to automatic scheduling and resource allocation, the code must be written with behavioral coding style. I use in in some designs, the result is very interesting. But...
  9. azerm

    clock tree spec and buffer list

    during synthesis, you mut specify clock ports as ideal network with appropriate command (like set_drive 0), so synthesis tool does not insert any buffer for these ports.
  10. azerm

    What is common use file format for I/O pads in ASIC flow ?

    i/o asic pad Hi, PAD insertion in ASIC is very differenent with FPGA. There is no good way for automatic pad insertion, instead designer may put each PAD in the top level netlist same as other blocks. Also other PAD issues like power & ground, multi_supply pads, ESD rules, filler and breaker...
  11. azerm

    synthesis using cadence

    sdc_write_unambiguous_names Is this flow ok with BG?
  12. azerm

    Help for Tetramax on SuSE 9.1

    Does anyone installed Syn0psys Tetramax 2003/2004 on SuSE 9.1 I installed it in both overlay and standalone modes, but everytime when I run it, gives SEGMENTATION FAULT error. I installed other synopsys 2003 tools on SuSE 9.1 and the work well. Can anybody help me?
  13. azerm

    Problem with models for Varistor and LM339 in Proteus library

    no model specified for u1:a LM339 does not have a LISA or SPICE model in proteus 6.7 SP3. So it cannot be simulated anyway.
  14. azerm

    A question about temperature

    It is just a question. I dont know if there is any practical example. As I know, in high temps. (ex. +125 oC) the devices are modeled for corner simulation for stress or life cycle test. So what is the behavior of semiconductures, specially CMOS devices in very low temperatures? Are the PDKs...
  15. azerm

    110/220 AC to 5/12 DC without Transformer

    power supply without transformer Hello, I need a circuit for 5v/12v DC supply from 110/220 AC. The common way is to use a transformer, a bridge and a voltage regulator. I know this way, but it is needed to be done without using trans becasue of its weight. The maximum current is 500 mA. A...

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