Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by Azaxa

  1. A

    Verilog Quad 7-seg display

    Thank you for the advice. I implemented the combinational logic as opposed to a purely clocked system and that has solved the issue where the 7-seg displays 2 clk cycles after s. I'm not entirely sure why it now accepts that there are no multiple drives for val2/3 as they are both in separate...
  2. A

    Verilog Quad 7-seg display

    P.S. I removed the always@ (sw) and placed it all in the always@ (posedge clk) block which i believe removed the multi-source error but gave the exact same errors as example 1 and 2 in the first post. It's a problem with the procedural assignments on the shift register but any procedural...
  3. A

    Verilog Quad 7-seg display

    I tried a few variations of formatting the blocking/non-blocking assignments and all of the outputs are registers including the output from the decoders but the same error persists ERROR:Xst:528 - Multi-source in Unit <test> on signal <val0<3>>; this signal is connected to multiple drivers...
  4. A

    Verilog Quad 7-seg display

    Ah right. Analyzing my code it looks like this is what i'm doing from a block diagram perspective. Placing the always block in the entire circuit causes errors with the other always@ blocks inside of the "always@ (posedge clk)" block. And I used the binary-BCD code on the second example for...
  5. A

    Verilog Quad 7-seg display

    This was done completely on my own through exercises from University :S but if that's the case I can see why you'd think that. Thanks anyway
  6. A

    Verilog Quad 7-seg display

    I am creating a Time-Multiplexed Quad Seven-Segment Display where the last 2 digits of the display, AN2 & AN3, show the decimal value 00-99 from an input of 8 switches (ignoring values at 100+). I have a few examples of code where the output on the display is correct according to ISim but with...
See more

Part and Inventory Search

Back
Top