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Recent content by ayza1505

  1. A

    2 dimentional array memory declaration

    Re: need help:verilog ram i dont understand.for example?
  2. A

    2 dimentional array memory declaration

    Re: need help:verilog ram so i need to modified in the different blocks for ado_data_reg?
  3. A

    2 dimentional array memory declaration

    need help:verilog ram i tried run this program but there's an error because of memory:multiple constant drivers.anyone can help me??? input WEN, A0, A1 ; input DI0, DI1, DI2, DI3 ; output DO0, DO1, DO2, DO3 ; parameter MEMORY_SIZE = 4 ...
  4. A

    need help to convert vhdl code into verilog

    converting vhdl code into verilog i tried to convert this file into verilog but it cant works!!there's a few things missing.i guess so.pls help me... LIBRARY ieee; USE ieee.std_logic_1164.all; Entity d_ffdelay is port (clk,resetn,d_in: in std_logic; d_out : out std_logic); end...
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