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ata target
Hi,
I'm doing a dram based ramdisk/harddisk - and right now I'm looking to implement a PATA controler (in a spartan fpga) - anyone has done that here / can give me some good reference or even some ip-snippets ?
measuring output impedance lvds driver r0
Hallo Frank, ;)
yes that's correct - I have found nothing similar in TIA 644. Anyway that is also quite suprising to me because if you hardly any common-mode-signal termination than you just rely on the damping of the line for disturbances.
Meanwhile...
damping resistor on lvds
yes the ieee states some testing measures - but come on - they have a 33nF load for testing ;) - if you let this load see an active feedback circuit - you will detoriate the way the feedback works so much that you will realy get nothing what is of any use ...
irf you have something like an ideal_balun this would be the way of choice to do it in a more elegant way - otherwise you can also make an ideal_balun by yourself as a subcircuit ...
I'm designing a CMOS TX driver. It has anupper and a lower biasing current source. By controling the current sources the common mode voltage is regulated as described in the Boni paper.
Now I figured out that there is a seriuous problem with the stacked 4 nmos-switches which "guide" the...
cmos to cml
Hi,
I need help - I have a (differential) cml buffer which drives the output driver stage of a lvds TX driver. Now I would like to have a stage before the ml buffer which converts the data-signal which has cmos-logic-level and is single-ended to the differential potential that is...
Re: LVDS design
concerning the jitter - as jitter depends on the noise created in the TX driver stage you can do a transient noise simulation with mmsim/spectre from cadence - if you use cadence tools ...
after running the transient noise simulation with a pseudo-random-bit-generator or just a...
Hi,
I have run a transient simulation for a selfbiasing circuit in order to let it swing into the "normal" operating points. The (transient) operating points are saved at the last time step.
Now I would like to use these saved operating point information for the initialization of another...
Hi,
I'm looking for ways to generated to complementary/inverted rail to rail signal from an incoming clock signal - in order to get a pos clock and a inverted clock signal. Whatis important is that the skew between the signals should be below 50 ps in a 0.35 um process.
I have problems to...
well - as the g0 of the pmos and of the "cascode" are in parallel in the small signal model - the pmos g0 would dominate the B*gm1*(g0upper||golower) - so there would be nothing to gain by having a nmos cascode and only one pmos towards vdd ...
Added after 5 minutes:
vut when we are into...
Hi,
could someone please be so kind and post the equivalent small signal-model of the symmetric cmos ota ? I'm a little bit puzzled right now ...
Thanx and merry christmas ...
cmos regenrative latch ieee
Is there realy no one who has ever designed a fast continuous comparator and tried to optimize it not just for hysteresis but also for speed ???
how to design regenerative latch
Hi,
I've just read Gregorians book "CMOS-Opamps and Comparators". In chapter 8.3 he introduces to a sample design of a regenerative latch based comparator with hysteresis. On the last page of the chapter (p. 354) he adds that one might optimize the sizing of...
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