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Hi,
when iam simulating my patterns. i got few errors. the errors are like simulated 0 expected 1 at some pins. can anyone explain why these kind of mismatches will occur?
After performing ATPG , i got the fault coverage and test coverage but fault coverage is less. Can anyone help me on how to resolve issue . The issue is with unused pins in the design. The fault coverage is less due to UU (Un used ) fault.
thanks for your reply, but I have used Synopsys design vision for generating netlist. I want that to save as txt file so that ican generate graphs and after I can use other algorithms for topological sorting. how can I do it?
hii friends,
This is code i have written for combinational parts of s27 circuit. i think it is not the exact procedure to write plz help me wheather it is correct or where i am getting wrong.
module s27(G0,G1,G17,G2,G3,G5,G6,G7,G13,G10,G11);
input G0,G1,G2,G3,G6,G5,G7;
output G17,G13,G10,G11...
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