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Recent content by atulaxc

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    Prime IMplicant & Essential Prime implicant

    Final product term obtained from K-map after combining all possible adjacent squares is known as Prime Implicant. What are Essential Terms ? When one Minterm can only be represented by one Prime Implicant then it is called essential term. Why it is required ? It helps in determining other...
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    [SOLVED] rising_edge() of switch....can we

    Provide some more details .. insufficient .. are you coding some logic to detect that?
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    digital interview questions with answers?

    That's always difficult to find answers to asic/fpga digital design interview questions. Following site has a decent collection of design questions and answers or hints to links to find complete answers. https://www.fullchipdesign.com/interview.htm
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    clock gating - implementing ICG cell

    this link has more details **broken link removed**.
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    4 bit full adder in verilog

    Always better to know some basics for the circuit. In case of a full adder we can implement it using two half adders and one OR gate. Verilog code and circuit details here Verilog rtl code for full-adder Full-adder circuit discussion.
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    FPGA related question.ALTERA kit is used

    Verilog rtl coding is not so difficult assuming you already have some coding background. Try this online tutorial. Good luck!
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    Intel 8051 Verilog Code

    You can check following link with details on **broken link removed**
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    clock gating - implementing ICG cell

    AND gates can result in glitches, so not recommended. But if you think design can handle the glitches then you can do an eco in synthesized netlist or change in rtl to insert a AND gate and then make appropriate connections.
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    [PLL] What is free running clock

    Free running clock is not part of any standard. This is just a way of showing the independence in phase relationship of a clock on a chip to other clocks. The PLL's on chip can used free running clocks as input to generate fixed output clocks. This link has details on PLL.
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    Parametrization in Verilog, sized and unsized vectors

    This is another way Refer example from this link for (i=0;i<64; i=i+1) memory_ram_q[i] <= 0; end
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    Positioning Reference Signals LTE

    Here is a good reference https://www.fullchipdesign.com/tyh/4g_lte_reference_signals_pilot_demodulation.htm
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    plz help me i hate to submit before 30th of this month

    See if this gives you some background to solve the problem shift_logical_circular_arithmetic
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    LTE OFDMA PRBs and LTE phsical layer farme

    From this reference: lte_downlink_generic_frame_mimo Frame Duration = 10 ms or 10/1000000 second. One Frame has 10 sub-frames. Sub-frame duration = 1 ms or 1/1000000 second. One Sub-frame has 2 time slots. One Time slot = .5 ms or 1/2000000 second. Each Time slot contains 7 OFDM symbols with...
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    Error in Verilog problem

    With reference to sync_memory explanation on **broken link removed** You can infer RAM on fpgas by just removing the reset condition from the always block.**broken link removed** the memory is going to be inferred using logic cells.
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    direct instantiation problem

    when synthesis works fine: I guess its still not reading the component from library. Instead its picking it from your component declaration. Are you sure the component resides within the library?

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