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Recent content by atlaakreddy

  1. A

    layout versus schematic verification

    normal netlist means .v
  2. A

    layout versus schematic verification

    give one example of schematic netlist and normal netlist
  3. A

    layout versus schematic verification

    what is the difference between the spice netlist,lvs.v,schematic netlist?please expalin withe detail? what is the formate of spicenetlist, normal netlist, schematicnetlist, lvs.v?
  4. A

    Antenna rule checks in the physical verification

    how antenna diode acts? like rc low pass filter r rc high pass filter?can you explain detailed way. iam new to learn the course plase help me
  5. A

    Setup and Hold checks

    What happens if setup and hold checks are not done correctly? please explain with an example, I am new to STA.
  6. A

    Clock Gating Check in STA

    1) I am new to STA. I know that Clock gating is used to save the Switching Power by shutting down the clocks to the registers when not needed. But if there is an inverter in the gated clock signal just before it reaches the sink pin of the registers, the inverter will turn the clock signal to be...
  7. A

    clock tree sysnthesis

    Re: clocktree sysnthesis iam learning course present ....so i have no document ...please send me any document related that........... [email address removed] - - - Updated - - - presnt i am useing encounter tools please help
  8. A

    clock tree sysnthesis

    clocktree sysnthesis how iam wrote specificationfile...based on that file i have to build clock tree....please help me clearly
  9. A

    clock tree sysnthesis

    [moved] clock tree sysnthesis specification file if i modify specification file as my wish then i will build clock tree but i cant get ...it will load previous on as i got.how iam got what iam changing based on changing im expecting output ..iam getting ouput based on my changes please help
  10. A

    What is an antenna violation? When will it occur?

    Re: what is antenna violation? wen it will pccur? what is planarization steps?
  11. A

    What is scan.def file, why it is used? What kind of information you will see in the scan?

    Re: what is scandef file why it is used ?what kind of information you will see in the yes ....iam asking what it contains tell me clearly
  12. A

    clock tree sysnthesis

    1.how to generate clock tree specification file [if top level guys is not giving]? 2.what kind of information will have in spec file?
  13. A

    What is an antenna violation? When will it occur?

    what is antenna violation? wen it will pccur? what is antenna violation ?what we take care of it
  14. A

    data trans violation is 50 ps then can we go ahed?

    there is no setup and hold violations but data trans violation is 50 ps then can we go ahed ?if go further tell me the reason? if not tell me the reason?
  15. A

    What is scan.def file, why it is used? What kind of information you will see in the scan?

    what is scandef file why it is used ?what kind of information you will see in the sca in scan.def file contain what kind of information will you see can you expalin detailed way?
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