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Recent content by atena

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    Visual Studio and Gcc remote control

    Dear everybody. Can anyone help me to solve the quite simple problem. I want to write a program to control the CD-ROM from a remote desktop. (1) If i input a number say '1' : The CD-ROm drive will automatically eject. (2) Else if i input '0': The CD-ROM drive will automatically close. I...
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    Using LWIP of Xilinx EDK

    lwip xilinx Dear all of my oversea friends in EDA Board community. I have stucked with the LWIP with no way out for nearly 2 weeks, and really do not know what should do. Previously i found that the Xilnet and Xilsock is extremely easy to operate, but with Xilinx 10.1 ( the new upgrade one...
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    PLB Master module is not operating correctly (250 points!)

    xio_in32 bram Can you upload your whole design so that i can have a proper check.... Thanks
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    Need help immediately regarding RS232 programming

    Dear everybody I'm a quite new bee in C++ programming to interface and control PC's peripheral, here my target is RS232. I want to write a program for a PC to continously send data to Rs232, can anybody give me a sample program ? Or give me a guide, which package header i have to use to clearly...
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    What is \***SEQGEN***\ in synthesis of netlist using Design Compiler?

    Re: synthesis of netlist This \**SEQGEN**\ elements appear when you forget to amp your design with link library ... Give the proper Link and Target Libraries and after "Analyze" and "Elaborate" you have to issue "Link" and "Compile" commands ... After that those SEQGEN will be removed ...
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    different of libraries

    Refer to Library Compiler & Design Compiler & Power Compiler for more details ... The simplest explaination is : Library is nothing but a dat bank where you can pick up the essential information for your design ..
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    relation between static power dissippation and speed of opat

    Re: relation between static power dissippation and speed of This answer is correct ... Static power is the nothing but a leakage power when circuit is in OFF state so it's independent of operating frequency ... Only the Dynamic Power increased along with the increment in speed ...
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    How to generate sdf using max & min libs so sdf will consists of corresponding delays

    Generation of sdf Either Design Compiler or Prime Time can do it .....
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    Recommend VHDL and Verilog Handbook

    Uhm, this book seems to be very good, at least it is better than all the HDL books i have read til now .... Quite good update ....
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    Nanosim Power Simulation

    synopsys nanosim vector input Ok, now i quite get your question , the problem is that you have to change the data in your vector file sequentialy or you already have 1000 ready made vector file ? Case 1: If you have only 1 vector file and have to change its datas urself, that case i dont...
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    VHDL to schematic conversion

    If VHDL to Schematic only, XILINX can handle it by View RTL Schematic option. If you want to get a VHDL netlist(gate-level) design, use Design Compiler...
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    hold time calculation

    What happen if someone ask you "From which heaven we can pull those datas such like Setup,Hold time down and put them into our libraries?" my friend .. :D ... Ha, i'm just kidding... In fact you are right, those datas must be listed in our design libraries, but the library designer(not us) must...
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    Nanosim Power Simulation

    vector file spectre netlist Spectre ? If i do not mistake it is a CADENCE tool ... You want to use its netlist for SYNOPSYS NanoSim ? Regarding your original question, i think i have quite misunderstood a bit, script nesting may not help you much if your no of simulation is greater than 1000...
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    Nanosim Power Simulation

    nanosim power simulation Using nesting with script and configuration files and save the result with diffenrent names in stead of NanosimPower only in a seperated folder.
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    VHDL to VERILOG CONVERTION

    from vhdl to verilog free converter Compile your VHDL code with Design Compiler and convert it into VHDL gate level design, unparameterized the parameters by [-param] option during elaboration, and finally rewrite the code in Verilog by issueing the instruction Write -format Verilog ...

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