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They are 2 different devices. For PA you need to use 3.3 volts.
we have both 1.8 and 3.3 volt transistors, one for low and another one for high voltages.
With 1.8 you cannot get a good output power.
I will connect this stage to others to construct pipeline ADC.
Since we produce bits at the output and convert them to decimal manually using a code, it should not be a problem.
voltage spikes wont effect bits I think since they occur for a very short time. (I hope so)
we use final decimal...
I did this already to my switch.
First of all you can define open and close resistance to your switched.
I also added capacitance (Cgd - Cds - Cgs)
still same problem.
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Adding capacitors and making Ron=50 Roff = 1 MEGA
I wrote Vg DROPS to vth. In class A minimum Vg is Vth.
I explained it very clear with numbers. you need to check swing that is it.
VDG = VD - VG < 3.3 (not dc values, signal swing)
better say VDG(max swing) = VD(max) - VG(min) < 3.3
I did some tapeouts with 180nm so these numbers are real.
I cant write verilogA for the whole system it is too much. I am not very good with verilogA
I wrote a code for only switch and it does not converge for some reason.
There is NO current flowing through Rf. It is connected to opamp V- which has 0 current and conneted to Iac which has 0 dc.
So current has no where to go ! other side of RF is like open
Do you know opamp inputs do not sink/source any current ?
I would suggest to make a single input opamp. That makes your work easier.
Honestly i have not seen this kind of configuration for TIA. Its whether differential input different output or single to single
Check this
https://www.ece.tamu.edu/~spalermo/ecen689_oi/lecture5_ee689_tias.pdf
So...
you need to design driver with the output power that is needed at the input of your second stage --> Pout 1dB (driver) = Pin (PA)
Then you will find optimum ZL and you have optimum Zs for your main PA you have found from source pull
design a matching circuit that matches ZL(driver) to Zs* (PA)...
You will have linearity problems if you have very high gain at input.
Imagine you use other stages after these amplifiers, the total IIP3 of chain is:
1/IIP3(tot) = 1/IIP3,1 + G1/IIP3,2 + G1G2/IIP3,3 ....
It means that the next stages should have extremely high IP3s to achieve reasonable...
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