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I have download this .zip too.
And I can't draw constellation too.
Like I undestand after start modelsim.tcl must be open new window with constellation plot. But I don't see new windows. Only usual signals.
Does anybody have other possibilites for show constellation in modelsim.
No I not have any counters that can overflowed. I am tested whole my design for find this. If I have counters it is overflowed very more time in one minute.
I not said that frequncy about 150MHz. But chip very quick (-3)
All signals in one clock domain. I am not describe situation in...
There is a big problem with determining the cause very strange bug:
Project in the crystal Xilinx works fine, but from only 7-10 hours and then one part of it hangs.
Now the details: By many experiments revealed that error inside the trigger of Xilinx chip (ie the output signal ceases to be)...
AD9863
I am use AD9863, and have problem with it.
I am use it in Full-Duplex mode with inner PLL.
I looking on RX data flow. When I reset AD9863, I see that after it RxA and RxB in data bus "L" shuffle (exchanges between itself).
By oscilloscope I look on MSB of data bus "L", IFACE2...
You need find correlation of each part of image. Or find two dimension correlation, but this is the same. If your area can rotate and/or scale you need use affine transfer for your unique area.
The same operation use fractal encoder.
You need to use constraints and try to increase number of pipe-line registers.
You can try to see your problem in FPGA editor or PlanAhead and it will give your idea.
super resolution
You can try to find it in google:
https://www.stanford.edu/class/ee392j/Winter2004/projects/Deepesh/ee392j_project.doc
**broken link removed**
I am upload this https://opencores.org/project,workwithfiles
I think that make test blocks with ce and clk this is very good for future arhitecture of whole project
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