Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by asjohnas

  1. A

    Openings in MNC in digital

    I am interested. I have made very more cores and testbenches(I am working more than 5 years) I am looking telework.
  2. A

    How to read VCD in Verifault ?

    In modelsim you can load it in vsim. You point what nodes you reload by VCD.
  3. A

    TEXTIO : Parameter L error message

    I have made read in vhdl: https://opencores.org/project,workwithfiles
  4. A

    Tcl/Tk Constellation Plot Display for ModelSim

    I have download this .zip too. And I can't draw constellation too. Like I undestand after start modelsim.tcl must be open new window with constellation plot. But I don't see new windows. Only usual signals. Does anybody have other possibilites for show constellation in modelsim.
  5. A

    variable question in VHDL

    Variable this is definition your task like combinatorial logic. For correct synthesis of it you need connect this combinatorial logic to triger.
  6. A

    Very strange bug with Xilinx

    No I not have any counters that can overflowed. I am tested whole my design for find this. If I have counters it is overflowed very more time in one minute. I not said that frequncy about 150MHz. But chip very quick (-3) All signals in one clock domain. I am not describe situation in...
  7. A

    Very strange bug with Xilinx

    There is a big problem with determining the cause very strange bug: Project in the crystal Xilinx works fine, but from only 7-10 hours and then one part of it hangs. Now the details: By many experiments revealed that error inside the trigger of Xilinx chip (ie the output signal ceases to be)...
  8. A

    Need help to solve AD9863 problems

    AD9863 I am use AD9863, and have problem with it. I am use it in Full-Duplex mode with inner PLL. I looking on RX data flow. When I reset AD9863, I see that after it RxA and RxB in data bus "L" shuffle (exchanges between itself). By oscilloscope I look on MSB of data bus "L", IFACE2...
  9. A

    TMS320TCIxxxx modul RSA(Rake search accelerator)

    May be somebody have documents, about instruction-set for RSA co-processor (Rake search accelerator) that include in TMS320TCIx ?
  10. A

    Finding Unique area in an Image

    You need find correlation of each part of image. Or find two dimension correlation, but this is the same. If your area can rotate and/or scale you need use affine transfer for your unique area. The same operation use fractal encoder.
  11. A

    VHDL CODE FOR UART URGENTLY NEEDED

    You can go xilinx web-site and get picoblaze. Picoblaze have sample with UART.
  12. A

    How to reduce route delay???

    You need to use constraints and try to increase number of pipe-line registers. You can try to see your problem in FPGA editor or PlanAhead and it will give your idea.
  13. A

    i want help with super resolution using gerchberg algorithm

    super resolution You can try to find it in google: https://www.stanford.edu/class/ee392j/Winter2004/projects/Deepesh/ee392j_project.doc **broken link removed**
  14. A

    vhdl code to call data from .txt file

    I am upload this https://opencores.org/project,workwithfiles I think that make test blocks with ce and clk this is very good for future arhitecture of whole project
  15. A

    2's complement of sine wave...

    You should see http://en.wikipedia.org/wiki/Two's_complement

Part and Inventory Search

Back
Top