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Recent content by asicer

  1. A

    DFT papers - pdf files to download

    DFT papers papers on DFT
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    Which HDL are you using? plz choose or state

    Which HDL are you using? plz choose or state.
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    manual about verilog PLI with some examples

    on Verilog PLI a manual about verilog PLI with some examples
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    Farzad Nekoogar on ASIC Timing (one chapter)

    It is good. will you please post other chapters of the book?
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    asking for comment on 2-phase clock, latch design style

    Does anyone has experience with ASIC design with latch and two phase clock? I though it may save area using latches. The two phase clock scheme can handle the timing problem with latch. What I don't know is whether it can be employed in the ASIC design flow using Synopsys tools. Would anyone...
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    what is a buffer and other questions

    more questions I took "courrant amplifier" as "current amplifier". Did I make it right? I learned a pair of inverters could be used as a buffer when I read Synopsys books. Can anyone tell me where to look for more info about the structure, attribution of the buffer, like the Synopsys...
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    what is a buffer and other questions

    what is a buffer? When Synopsys says a signal is buffered (such as the clock), what is added to the net? Is the Buffer a pair of inverters? Any other structures?
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