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There is a an option "+no_neg_tchk" in vsim. I suppose if you don't use this option, vsim will accept negative values.
Even if vsim will never accept negative values, I think the negative value is usually very small, and we usually have additional setup/hold timing margin at STA (note, this...
I think this is just an industry stander. We can define it at 5% difference.
But 5% difference will be more difficult to meet as there are some variations: power supply, IR drop.
So, this may cause additional cost to meet this requirement.
To my understanding, DC can't insert DFF for pipeline purpose. This will also causing LEC problem.
I think you have to insert DFF to do the pipeline by yourself.
1): setup / hold are calculated at the point which the clock and data reach at the DFF clock pin and data pins. And there will be delays in the DFF cell itself on both clock and data pathes. For negative hold time, you can image there is a large delay within the DFF cell on the data path (so...
To my understanding:
--- Start Point ---
1): Top module inputs (not sub module inputs)
2): The clock pin of a DFF/Latch
3): clock network (use the clock name when you define a clock)
--- End Point ---
1): Top module outputs (not sub module outputs)
2): The D/Enable/SYNC reset pin of a DFF/Latch...
I think one easy way maybe, wirte a RTL wrapper for that sub-module.
Just define the input/output and assign all the outputs to a constant value. Then, your problem will gone at both simulation and synthesis.
This will disable all the hold check.
This SDC maybe used by synthesis, not by Place&Route and PT check. This may because: hold violation are usually fixed at P&R phase, not synthesis phase.
Usually, you can tie it to "OKAY" all the time, if:
1): The slaves on the APB bus will never generate "error" response (that means every r/w transfer will success). This is usually the digital circuit does.
2): The slaves on the APB bus can response the r/w access quickly enough to met your AHB...
Data within DDR PHY.
Need shift the DQs to capture DQ (named as dq_reg), then, dq_reg will be transfered to clock domian in the chip (this can't be a flase path while transfer between 2 clock domains).
It's usually the delay of wires are very small. And the delay numbers reported by DC just has 0.01ns precise, by default. Then the wire delay will be shown as 0.00 (0.0001 -> 0.00)
You may see the delays by:
1): Write a special RTL code, make one wire has a lot of load. --> 2): change the number...
To my understanding:
1): you need set "set_propagate_clock [get_clocks clki]"
2): you need specify clko as ideal network, as you are doing RTL synthesis, no clock tree now. Maybe something like: set_ideal_network [get_pins clko_reg/Q].
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