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Recent content by ashutoshdeenanath

  1. A

    Trouble Understanding .noisetran simulation results in eldo

    Re: Trouble Understanding .noisetran simulation results in e Hi Plz run the simulation for more time. u will get KT/C for 1 pf ~ 64uv.
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    Looking for UART Verilog model

    opencores uart u can get verilog code from here https://www.asic-world.com/examples/verilog/index.html
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    Uart design in verilog

    u can find uart verilog code from here below https://www.asic-world.com/examples/verilog/index.html
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    poly and well resistor?

    hr poly resistor poly reistor have not high resistivity its accuracy will be best than others. the high resistivity resistors are HR poly or well resistors.
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    Question about pad and bond pad terms

    pad or bond pad? pad always contains esd structures also so its size will be more than opening. 1 will define the opening of the pad after passivation . 2 will define the size of the pad. 3 will define the minimum spacing between two pads.
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    What does nitride edge mean?

    nitride edge? fox used to make seperation between devices on substrate. but the hight of this fox will be apprx. 6000a . this much hight can not eatch. so to avoid to grow the fox on the active area , active area can be defined by nitride. fox can not grow on nitride and there will be a small...
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    Twin well cmos process

    twin-well process I think CMOS technology process is twin well process. bcoz if u want to fabricate pmos in p substrate u need a nwell simultaneously when u fabricate nmos u need to pwell. this pwell is not defined by layer but the same layer of nwell can used with negative photoresist, means...
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    Input resistance in a pad

    generaly there are two type of pads used in IC designing. input and output pads. generally input goes to the gate of mos and output comes from drain or source. to prevent gate from ESD we use diode protection simultaneously with resistor. if input or output does not goes to gate any one can use...
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    Need to design Pipelined ADC

    there many kinds of calibration schemes for 1.5b/stage pipelined ADC! if you want schematics, I am afraid there are not much on web! some IEEE papers may be helpful: "Digital_Domain Calibration of Multistep Analog-to-Digital Converters" "Background Digital Calibration Techniques for...
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    two different guard ring

    guard ring A is better bcoz substrate will same and noise will come from substrate and if guard ring is break then it will create problems
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    How to simulate pmos i-v curve with hspice ?

    lv9 hspice mp d g s b p w=20u l=2u *********** FORCES ********* vd1 d1 0 dc x vg2 g2 0 dc 4v vs2 s2 0 dc 5 vb2 b2 0 dc 5 ********* ANALYSIS ********* .op .tran 1n 10n .dc x 0 5v .1v ****** VT CURVE******** .print 'VT_P'=LV9(mp) ******IDS_VDS CURVE******** .print...
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