Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by ashutosh_g

  1. A

    VHDL code for debouncing the reset signal

    i use a push button for giving negative reset to my FPGA. The push button however is bouncy. can any one give me the code for debouncing the reset signal. so that the internal reset signal goes to zero only once for a stipulated amount of time after pushing the push button. I need the code in vhdl
  2. A

    debounce code push button

    i use a push button for giving negative reset to my FPGA. The push button however is bouncy. can any one give me the code for debouncing the reset signal. so that the internal reset signal goes to zero only once for a stipulated amount of time after pushing the push button . I need the code in VHDL
  3. A

    References about writing synthesizable code (HDL design)

    I have some expirence in HDL desgin but i want to gain strong basis in writing synthesizable code can any one suggest me any ebook on the same ... specially thinking in hardware ...
  4. A

    How to preserve a node named data in Quartus II?

    Quartus II In my design i have a node named data which is removed during the synthesis what should i do to preseve this name so that the Quartus-II synthesiszer doesnt remove it. I tried preserve port name in the Assignment editor menu but it did not work regards ashutosh
  5. A

    Recommend me the best free VHDL simulator

    i need a free vhdl simulator can any one tell which is the best one and where to download it from
  6. A

    Quartus II error message

    i am new to quartus i was compiling a basic VQM file of 8 bit adder. I generated the VQM file from FPGA vision (Synopsys). i am getting the error message Error: WYSIWYG LCELL primitive "sum_reg_3_" cannot use datad port when in arithmetic mode can any one tell me please what does this...
  7. A

    Good books on RFICs meeting todays technology

    try razavi RFIC design its good
  8. A

    Books/papers about PLL Loop Dynamics

    Re: PLL Loop Dynamics deans book is good but very detailed :) try "texas insturments swra029" google for it you willl get it online if not let me know your email i will send it over
  9. A

    How to calculate frequency resolution of a PLL?

    dds pll well yes i am looking for frequency accuracy i want to know accurate can a frequency be from a PLL. is it mHz Hz and how to calculate it ...i dont want to use DDS :)
  10. A

    How to calculate frequency resolution of a PLL?

    how can i calculate my frequency resolution of PLL ? will i able to generate frequency up to Hz mili-Hz or micro-Hz etc with PLL
  11. A

    buying Bandpass filter

    you can search for components at: rface.com you will find all the vendors there
  12. A

    PLL phase noise question

    if i understand correctly than by inband you mean the noise inside the loop bandwith of loop filter ..right ? since VCO and its phase noise is always there at the output this means that PN due to VCO will be there however if the loop is closed you can actually get bettter performace than...
  13. A

    PLL-comparison frequency

    i have to design a 3.4GHz frequency synthesizer with a PLL. i am using LMX2487 by national.. i dont have to switch my frequency (its not for wirless communication) to reduce spurs i want to keep by comparison frequency as high as possible in this if i use a crystal of 10MHz can i use it...
  14. A

    Synchronous data transfer on AT90S2313

    snycronous data transfer i need to program a PLL synchronously with a 100ns clock . is it possible to do so on AT90S2313 ?
  15. A

    How to generate a clock using AT90S2313 ?

    AT90S2313-help i need to program my PLL using AT90S-2313 for this i need to generate a sequence of bits a clock and and load enable signal can any one tell me how can i egenrate the same clock should be of 100ns period
See more

Part and Inventory Search

Back
Top