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Hi I tried to compile the testbench in a different library as ads-ee suggested (actually I think I could not understand fully what ads-ee said) but still no luck --- same output as before,
Pls somebody give me a short video tutorial how to do ?
Please help me
thanks and regards
thanks to all I took add1 above stimulus in my testbench as Akanimo suggested, I also removed the component declaration and used
, even I made my design and library name as 'work'
but still no luck:-(
I don't know what to do??
please help me
Thanks for fruitful replies, I used "std_logic" as std_match suggested but still no luck,
this is the updated and.vhd with "std_logic",
this is the updated testbench and_tbench.vhd with "std_logic",
and the output:-(
you were right, If out_c isn't connected it will show as "U" (not...
Hi all,
I am new to Active-HDL. I am starting to learn the tool by simulating a simple two input AND gate. The code is following,
--and.vhd
entity and_gate is
port (A,B:in bit;C:out bit);
end and_gate;
architecture and_gate_ar of and_gate is
begin
C<=A and B...
thanks ud23 for your reply, but your tutorial not worked I tried twice, but same error 6 in
AT+CIPSTART="tcp","raviyp.in","80"
OK
ERROR: 6
STATE: IP STATUS
Please some body help me
Hello all,
I am newbie using SIM300 GSM GPRS Modem and want to send data to my server,
First I got a net @G plan INR 5 = 20 MB on my AirTel sim
Then I inserteed sim in the sim slot, and connected my GSM GPRS Modem with 9600 baud, flow control none, 8 bits on Hyperterminal and issued the...
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