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I would like to discuss about resistor mismatch citing a very old post, even when I was not a student of Electronics. The post link is here: Resistor matching calculation
Let's say, I have two equal Resistor (R1, R2), 10k each, having a standard deviation (sigma ) is around 20. Therefore, the...
A good practice of designing OTA ( I assume here OTA, high output Z) is to keep the load as a non-dominant pole far from the dominant one which sets the gain and the BW. Following this, you will obviously ensure proper PM for your circuit. Hence, it would be applicable for different capacitive...
You don't need to calculate like that using textbook approach. the total calculated gate cap is termed as Cgg, (or Cgs), check the opamp parameters attached.
It seems there could be some issue on the method simulator follows to calculate the pole. I tried by myself and found a good match between hand calculation and simulator output. Here's using tsmc 180nm tech, I had to 'mimic' your TB. Therefore I used a bit more width than that of you.
and the...
What you are assuming, or the ground of hand calculation is simply RC based on the extracted DC. But the AC model of a particular technology is much complicated BSIM based model and could lead up to 300+ parameters. However there should be a near-match (may be 10%). Did you took Rout into...
Hi,
For many front-end systems (e.g. Wheatstone bridge) we need to measure only ratiomatric voltage. That means only the ratio as the signal. Now if the reference of the bridge varies, then is there any difference between ratiomatric error and gain error after a gain stage?
If I understand correctly, if you see in the design I_mn3> (I_mp1+I_mp7), [so, I_mp3=2*I_mp1], that's only due to the leakage. "Ideally" I_mp1 = I_mp7 for a folded-cascode can be employed. But if you require higher slewing or faster settling for some applications (depending on the cap or output...
Found the issue, it is related to the filesystem difference between Unix and Windows text format. The difference of "Line end Character" which has to be a newline (\n) creates the issue.
Hi,
I need some helps regarding reading a file (say .txt, could be .csv as well) from a directory path and then generate a voltage signal based on the array of values from the file.
There is a timing event, and the elements of the file array will be accessed based on timing events.
Here is...
Hi,
Is it possible to get an ac transfer curve of a sampled system with all desired sidelobes? I did a pac analysis of SC filter with 20 sidebands and found the behavior like this. But I am interested on getting the side-lobes as like as seen in the textbooks.
Please help.
The CMFB compares between your "output common mode" and "desired common mode" and feeds back a negative signal for regulation. The desired CM voltage you can generate by using a resistive divider from rail-to-rail, assuming your rails are already robust.
The CMFB used to give a separate DC CM gain at the output. Here you are sensing second stage output (which is indeed the "main" output) and regulating "any" internal bias node on a negative feedback. That's why the CMFB is applied for the whole circuit, don't need to think about the stages...
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