Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi Everyone,
I want to know what are different types of ENDCAP cells available in Physical Design and what is the actual difference between them?
Thank you.
Generally for soft blockages there is no flexibility to mention blocked percentage of cells, but for allow_buffer_only placement blockages there is a flexibility to mention the percentage of cells like if we mention 70% as -blocked_percentage, then buffer and inverters will occupy 30%.
while I am running CTS (clock_opt -from build_clock -to build_clcok), in the log file i am getting like this.
but those target skew values i already mentioned in the clock specification file with some other different values like this.
i.e., in log file i am getting target skew value as 0.75...
Hi, I've few doubts on SDC Commands
1. Is it possible to generate generated clock without having master clock?
2. If yes how to give the constraints to the generated clock and if we're giving constraints to generated clock, then whether these constraints are scaled for master clock?
okay if you want script I will send.
foreach_in_collection a [get_nets] {
set netname [get_object_name $a]
set netlength [get_attribute [get_nets $netname] dr_length]
puts "the length of the net:$netname is:$netlength"
}
select the net which you to find then use the command like
[get_attribute [get_nets net_name] dr_length]
or
[get_attribute [get_nets get_selection] dr_length]
Hi,
for example, if we missed to place the End Cap cells in your design, then what kind of violations it will show and where that violations can be caught i.e., in which stage and which check we need to do to find such kind of violations?
Hi All,
How many transistors are required for a single bit D Flip-Flop?
How many transistors are required for a 2bit D Flip-Flop?
and
what is the difference between single bit and multiple bit Flip-Flop?
How to calculate CRPR in Half Cycle Path and is there any difference between the CRPR value which we calculated in Full Cycle and the CRPR which we calculated in Half Cycle?
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.