Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
vhdl bidirectional delay
I need to insert some user defined delay on a bidirectional bus in VHDL. Ho wcan I do this?
I am using a delay inserting module as follows:
library IEEE;
use IEEE.Std_Logic_1164.all;
entity WireDelay is
generic (Delay_g : time);
port
(A : inout Std_Logic...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
