Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by AshkanYJM

  1. AshkanYJM

    [SOLVED] Verilog Error : Too Few Parameters Passed To Task

    You are right, The Codes Had Mistakes But I hadn't claimed otherwise, I just asked about those $readmembs. anyway I feel obliged to thank you both since you take time to check my poorly-written codes and type the errors and advice here. I really appreciate that. Well somebody come and make this...
  2. AshkanYJM

    [SOLVED] Verilog Error : Too Few Parameters Passed To Task

    Hey Guys, Long Time No See! It's been a while now, yeah I was too busy and as you can see(attached file) Things have changed, Revolution is here... It is very consuming to explain this, as I am sure you will understand what I have done(you know me) I just need to mention that clocks are not...
  3. AshkanYJM

    [SOLVED] Verilog Error : Too Few Parameters Passed To Task

    The last link worked great, much better than the BRAM PDF I read in CoreGen. Now I have chosen to use the simple dual port ram. two ports, 1 for in,1 for out, 2 clocks. exactly what I needed. Now guys, do you see this approach appropriate according to what has been said till now ? it's not the...
  4. AshkanYJM

    [SOLVED] Verilog Error : Too Few Parameters Passed To Task

    There's something here I don't get, about the bram a single port bram has these signals as pinout: CLKA:Port A operations are synchronous to this clock. ADDRA:adresses the memory space for port A Read and Write operations. DINA : Data input to be written into the memory via port A. DOUTA ...
  5. AshkanYJM

    [SOLVED] Verilog Error : Too Few Parameters Passed To Task

    I guess you are right. Read the attached pdf. It's very short and concise.
  6. AshkanYJM

    [SOLVED] Verilog Error : Too Few Parameters Passed To Task

    Read my code for circular buffer to see if I understand it or not.I'm not saying I need 40000 read points,I'm saying I need a memory anyway. maybe it's just a misunderstanding. you said no dual port memory is needed. But you actually meant it doesn't have to be dual port, a single port...
  7. AshkanYJM

    [SOLVED] Verilog Error : Too Few Parameters Passed To Task

    The base functionality of all these processes is in adding the current sample with a delayed sample. so the circular buffer and now the block ram with address generator is for this. to have two samples ready at a time to add or subtract. Well given a sample rate of 40 kHz at least...and...
  8. AshkanYJM

    [SOLVED] Verilog Error : Too Few Parameters Passed To Task

    I've been reading verilog all day... Guys, I'm feeling helpless, alone at the end of the world:-( I'm only 22 and not being able to proceed with my code I feel like dumb,and assume have wasted my life :-( Anyways, a man must fight for what he believes and I believe I can do this. Alright. Now...
  9. AshkanYJM

    [SOLVED] Verilog Error : Too Few Parameters Passed To Task

    x[n]+x[n-1] >>> Time-Domain X[Z]+X[Z]Z^(-1) >>> Frequency Domain These two approaches will give the same results but I am sure they are different.a FIR Filter works in Frequency Domain. It's all about Z^(-1) s! how can you say FIR is in Time-Domain ? unless there's a point i'm missing my dear...
  10. AshkanYJM

    [SOLVED] Verilog Error : Too Few Parameters Passed To Task

    I will procure that book and I will read it Day and Night. I'm not anymore into loops and tasks and cases and know that must do what you say. All my processes are in Time-domain, Do you think by going your way I still can stick to it and won't face Frequency-Domain processes ? It has to be done...
  11. AshkanYJM

    [SOLVED] Verilog Error : Too Few Parameters Passed To Task

    Not willing to change the program completely is because I fear it might take too long. Do you think I can Redo everything the hardware way in less than a week ? If so, Ready to go!! I built a true dual-port Block Ram using Core generator. I added it to my project, Now do I have to take it...
  12. AshkanYJM

    Designing LC filter for power converter

    There are many filters out there with different orders. I think Lmin differs from L0. Lmin is the least inductance needed for the filter to be a filter. L0 points out the typical L for that filter.
  13. AshkanYJM

    [MOVED] How to Get Electronic Job?

    Well any employer requires his/her employees have some qualifications. First you need to excel at English, be an expert in a relating Software or program, depending what you are supposed to do, be punctual, have honesty and commitment ... don't act helpless, No one can help you but you.
  14. AshkanYJM

    [SOLVED] Verilog Error : Too Few Parameters Passed To Task

    Yes, that's right. that's why My simulation does not return meaningful output because my output is in another module. even if I shorten my MUX into one module it doesn't do any good, I have to merge my MUX with circular Buffer in some way. when I used tasks There were only two modules, But I'm...
  15. AshkanYJM

    [SOLVED] Verilog Error : Too Few Parameters Passed To Task

    Uhum, Right. Now, I have a doubt that tickles me much. Do you think the program understands that the input [11:0]Buff_Array in that 4 modules, is the Buff_Array[k] from the circular Buffer Module ? To let you know, I had a simulation with verilog test fixture and the result was not good...
See more

Part and Inventory Search

Back
Top