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verilog assign
Hi All,
Can I use assign statement in verilog according to any active variable?
For example suppose I want to use assign statement if active( any reg ) is enable (say high active).
assign xyz = abc if (active ) other wise dont execute this statement at all.
Is it possible...
Hi all,
I am trying to implement one bidirectional bus. I am getting problem in test bench with INOUT port. Can anyone please suggest me that how to drive value in INOUT port in testbench.
My files are like this
v File
module check_inout(data, rw, clk );
input rw, clk;
inout [7:0] data...
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