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Recent content by ashish7724

  1. A

    Virtual channel router verilog or vhdl code

    @vGoodtimes I have three lanes of fifo. if(vcid==2'b00) data should be written in first fifo else if(vcid==2'b01) data_should be written in fifo 2 like this for vcid 3
  2. A

    Virtual channel router verilog or vhdl code

    can't i use tasks for reading and writing in code.... will it get synthesized?
  3. A

    Virtual channel router verilog or vhdl code

    could you plz help with some pseudi code or verilog code....
  4. A

    Virtual channel router verilog or vhdl code

    well..... I wanted to create virtual channels. Packet will be buffered in one of the four fifo (i.e. 4 virtual channel). Like virtual channel router. Shall I instaniate FIFO using generate or instantiateFIFO three times with different read and write pointer
  5. A

    Virtual channel router verilog or vhdl code

    I am designing a router with vitual channels..... I need help in what way I can design virtual channel buffer
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