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Recent content by asad_khan5130

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    4 bit register having parallel flip flops using VHDL

    any error in this code? entity reg4 is port(d0,d1,d2,d3, clr,clk : in bit; q0,q1,q2,q3 : out bit); end reg4; architecture structure of reg4 is component DFF port(D,clk :inbit; Q:outbit); end component; begin DFF0: DFF portmap(d0, clock, q0); DFF1: DFF portmap(d1, clock, q1); DFF2: DFF...
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    4 bit register having parallel flip flops using VHDL

    i could not find code on internet. can you please provide me code for 4 bit parallel register using instances of four flip flops.?
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    4 bit register having parallel flip flops using VHDL

    Thanks Klaus. but i want to make it using instances of four flip flops i have written this code. someone please verify it entity reg4 is port(D,clk : in bit; Q: out bit); end reg4; architecture behave of reg4 is component DFF port(D,clk :inbit; Q:outbit); end component; signal Q: in...
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    4 bit register having parallel flip flops using VHDL

    Thanks KlausSt. but I want to make it using four instances of D flip flops. i have written this code. can you please verify it. library IEEE; use IEEE.std_logic_1164.all; entity reg4 is port (d : in std_logic; clear : in std_logic; clk : in std_logic; Qout ...
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    4 bit register having parallel flip flops using VHDL

    Hello Everyone I am learning VHDL. i want to design a register with four parallel flip flops with common clock. can anyone help me in this regard?
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