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Recent content by Arthurzss

  1. Arthurzss

    Memory Cards specification needed

    Memory Card Those are what I am looking for. THX
  2. Arthurzss

    Template makefiles of Cadence LDV 5.0

    Cadence NC-SystemC How can it be ?
  3. Arthurzss

    Advanced Synopsys DC workshop

    Synopsys DC I think sold is enough for learning.
  4. Arthurzss

    Difference between FPGA and ASIC codes

    some question about ASIC Use library PADs in verilog code for asic. Use fpga tool to assign PADs for fpga.
  5. Arthurzss

    What does an IP core mean?

    meaning of ip IP is functional blocks which can be reused in many designs.
  6. Arthurzss

    Who understands timing in Verilog

    at time 100 and in line 6: and 9: the value of clk is '1' The clk should be scheduled to transition to one at the end of time multi of #100. The code you wrote is behavior code.
  7. Arthurzss

    Looking for information on co-simulation

    co-simulation Which kind of co-simualtion did you say, VHDL with verilog, or verilog with c?
  8. Arthurzss

    FPGA LUT to ASIC Gates

    asic gates I think use different tools to synthesize it and read the report will help you.
  9. Arthurzss

    Looking for book about Verilog coding style

    verilog coding You can find it in synopsys online document. There is a doc named Guide to HDL Coding Styles for Synthesis.
  10. Arthurzss

    to wadaye (about asic design)

    There is no simulation? post-layout simulation is very important.
  11. Arthurzss

    Verilog Compile Problem

    verilog expecting: ident [3] if the statement is empty, you should add ";" after it. And use "endcase" to end case sentence.
  12. Arthurzss

    How to see the simulated waveform in debussy?

    debussy waveform viewer nwave debussy You can dump the VCD file for Debussy to use: $dumpvars;$dumpfile("filename"); then use debussy to open it, it will be translate to fsdb format by Debussy automatically. Or you can use pli provided by Debussy when simuating, and dump fsdb file directly.
  13. Arthurzss

    How and where to start learning Verilog HDL

    Re: Verilog HDL Yes, you said it. And if you do more practice, you will master it more rapidly.
  14. Arthurzss

    Devide frequency into 3 using AHDL or Verilog HDL

    I use winzip 9.0, and it can decompress it.
  15. Arthurzss

    What is HW & SW co-design mean?

    There is many tool surppurt co simulation now. If you read the reference boot of it, you will see.
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