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chipscope finding signals
well i have found a way to see the signals in chipscope
use
KEEP constraint as
(* KEEP = "TRUE" *) wire dout_test;
this will keep those signal after sythesis optimizaton that were removed by the optimazation process
signals not in chipscope
hi Tan,
i m not talking about the instantiated signals,
but the instantiated MODULES.
These modules are FSMs (state machines) and i know for sure that its out put control signal are changing(bcoz my code is working fine), but i dont see my modules in the CHIPSCOPE...
keep signal and view in chipscope
tan,
thanks for the reply,
adding signal in port list works :)
but wat about my 2nd question, do u hav an idea
why cant i see the instantiated modules in the chipscope hierarchy
regard
arthur
chipscope hierarchy
hi,
i m using chipcsope pro 10.1 for the signal analysis,though i have successfully monitored quite a few signals in the design,
BUT when i insert the chip scope core using "chipscope pro core inserter" at the "modify connections" stage i m facing following problems
1- I...
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