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I use -mt command to make hspice run on several cores, it sometimes gets correct results faster than just one core running, but sometimes gets totally wrong results while I could get correct results by running on just one core. Why's that case?
Thanks!
I have thought that the function change may lead to longer critical path thus affect throughput, max frequency, or more logic unit as well as different switching factor.
Anyway, I think I need some experiments to verify what I think. Thank you for your answers!
Thanks.
Let me put it in another way. Does a completely different internal FPGA connection due to a minor functional change lead to quite different metrics measure values?
Bests
Well, I think my design does not use pipelined encryption. It does one encryption round per clock cycle and has two register blocks to store the states of input and output. Between the input registers and output registers are logic gates. Seems it is a synchronous design....
Bests
I think a security circuit must be an asynchronous design. I think these physical metrics much relate to the structure of the circuit, which is synthesized from a behavior verilog code. This means different structures from different codes will get different metric values.
I mean, the small change may lead to different energy or performance metric values, such as throughput, energy, power, etc, so this feature may limit the comparisons between physical metrics.
Not like structural Verilog code, a small change to behavior code may lead to huge modification of actual circuit, does this mean that this kind of implementation is not stable?
Thanks!
For example I have an encryption cipher, and want to implement the algorithm. I load the behavior verilog codes into FPGA and work it out. Can this process be called hardware implementation? I have thought that hardware implementation should follow the ASIC flow, which is at circuit or gate...
Hi tom,
Actually I think there might be two reasons, one is that there is not enough disk room for the simulation data, the second one is the version of hspice that matters. How about you trying hspice64 <input.sp> as the command?
Arthur
I need help with simplescalar platform. Can somebody give a link or descriptions to me
how does one modify the files, bpred.h and bpred.c in order to implement one's own
branch predictor? I know SimpleScalar is supportable to five built-in branch predictors, I just would like to know what I...
I copied another self-contained netlist file with Verilog-A path just in the same folder, but still the error above occurs. I am sure this netlist I copied is correct since it could run on my friend's computer, then is the problem within my computer or the access to the server?
I plan to construct the netlist file using Verilog-A model included in it. But during HSPICE compiling, it said
**info** *pvaI* system & gcc return code is 512
**error** *pvaE* Bad C code detected by TFET_Model_InAs.pvadir/pvaRTL.mak
**error** *pvaE* Please check...
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