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Recent content by art_man

  1. A

    A question about AMBA AHB

    master
  2. A

    When masters initiate transactions, how do they go to each slave in AXI interconnect?

    axi interconnect ip yes what raghu is saying is true. I am not sure about points I made previously can be useful in interconnect but to unify each master's ID there is something written in AXI specs. Address(or address range) can be used by interconnect for selecting the proper slave..as in...
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    When masters initiate transactions, how do they go to each slave in AXI interconnect?

    ahb axi difference 1) what i think is u need to design some kind of crossbar switch and priority what u can do is insert some own extra ID fields /tags of interconnect so that slave can get idea about which master wants to read/ write let say master 1's id 2 wants to write on slave no. 2's...
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    IEEE1149.1 controller

    u can get ARM's JTAG info on ARM's manual .. i have attached here a jtag from altera... there is info how tap controller is implemented inside a chip I hope it will help you.
  5. A

    What is the importance of PERL language for VLSI design engineer?

    Re: perl hi shiv, here is ref doc for perl might help u.. ~tejas
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    How to write test cases in Verilog?

    Re: Verilog Test cases hi vikas, I think u r from conexant..? done a course in ICIT , pune. i think for writing test cases u need to first understand the protocol on which you are working. U can refer some good books on functonal verifications for this purpose. After recognizing test cases u...
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