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It is possible use additional feadback to increase noise immunity, for example in pipeline ADC's MDAC we have feadback in phase of sampling but don't have feadback in phase of multiphlication. If we don't cut feadback in phase of multiphlication can it help me to increase noise immunity.
Output cap is 4.7uF, R=1k , when output reaches 1.8 voltage it must not change, bu continue increase.
I connect output with negative input of comparator, is it right ?
When i connect output wiht positive input, i dont get pulse in comparator's output. Vref=1.8v
Dear all.
I have dc dc converter step down without inductor, in switch capacitors. Input voltage 2.7-5.5, output voltage must be 1.8-1.9. When output reach 1.8 voltage PFM mode pauses the oscillator.But after that output continue increase because current of output capacitor goes through output...
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