Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Thanks for the reply. I'm trying to figure out who, what team, or which tool is defining the resolution of the CAD layout before the GDS/OASIS is generated. Perhaps my question was misleading with "design flow" -- I am actually referring to the compete IC design process, including...
Does anyone know at what point in the IC design flow the resolution of the layout is defined (i.e., OASIS file)? I have encountered multiple resolutions for the same technology node from the same foundry (TSMC 7nm) with resolutions of 0.001, 0.0005, etc.
Thanks,
Arpan Bhattacherjee
****email...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
