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Thank you for answer, and yes that's the problem, but there are few more requirements. In the future there will be eight DSP modules with 10 MHz output data rate, that's why output interface has to run with 80 Mhz - One data packet contains eight sets of processed data. Data with 10Msps rate...
The reason behind clock rate change is that data incoming to FPGA with 100 Msps are out of phase with 80 MHz clock, which will be send data out of FPGA. I want to move data into clock domain that is in phase with future 80 MHz and has common divisor with 100 and 80, so I pick up 240 MHz, which...
Yes, exactly! Data will be coming constantly in real time, so that was my idea to somehow transfer data to 240 Mhz domain in small chunks. Thank you, I will look into it.
Hello,
For the first time I deal with crossing clock domains (slow-to-fast) and I have faced a problem.
I recieve constant stream of data, which I have to filter, but before processing data have to move from 100 MHz to 240 MHz domain. I used standard asynchronous FIFO approach and I manage to...
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