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FvM u r my heroe :) thank u man. it works.
i understood everything u said. thank u. i spend so much time trying to make procedures, functions and many many other things to make it work :)
can u also propose me a good guide for vhdl because i'm trying to use shift operators and i have errors...
2 signal counter
FvM thank u very much for the reply.
You are right. i used "unsigned" and the compilation complited sucessfully. the bad is that it doesn't do what i wanted.. :)
-- ===========================================================================
-- Project : COUNTER_DEC
--...
cse.unsw.edu.au
hi everybody,
i'm new in vhdl and i'm trying to activate a signal after 12 cycles and then di-activate it again. for example,
start-0-0-0-0-0-0-0-0-0-0-0-0-1-0-end
i have these errors in Modelsim,
error: No feasible emtries for infix operator "+".
error: Type error resolving...
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