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Recent content by arena_yang

  1. arena_yang

    What is better for FPGA manufacturer, Xilinx or Altera?

    Xilinx or @ltera? Frankly, the two vendors' FPGA both can satisfy Dora's demand. But I think that Xilinx is better since its more flexible and easier-to-use features of the ISE software.In addition, the documentation of Xilinx is better,saving many development time.
  2. arena_yang

    HELP: HOW TO generate such timing

    According to the image, I want to generate the crc_scope according to the soc,eop and val. As we know,we normally get the falling edge by delaying signals two cycles and then to get the last two-byte pulse scope signal,just as shown in the image below. but how to get the signal for the image...
  3. arena_yang

    padding to ethernet using fpga

    Nobody knows? Or Nobody Will answer>!!!???
  4. arena_yang

    padding to ethernet using fpga

    In my design, I have to insert some payload in the PAYLOAD of ATM AAL5 CPCS PDU,so I will have to modify the length field and the PAD field of CPCS PDU tailer. But I have to recalculate the number of the PADding. So I want to know how to add pad ? If Anybody have experience with Ethernet MAC...
  5. arena_yang

    Help me recalculate the number of ATM PADding

    atm pad In my design, I have to insert some payload in the PAYLOAD of ATM AAL5 CPCS PDU,so I will have to modify the length field and the PAD field of CPCS PDU tailer. But I have to recalculate the number of the PADding. So I want to know how to add pad ? If Anybody have experience with...
  6. arena_yang

    How to protect the bitstream in Xilinx/Altera FPGA?

    Typically, If we use CPLD/EPLD, we can check the encrypt bit in the development software, but FPGA itself cannot be protected because of the SRAM architecture. I have one method to protect FPGA design: you can design a PRBS generator in FPGA and CPLD, the CPLD acts as the microprossor to...
  7. arena_yang

    RISC Processor design

    I have the source code of DLX,if need ,PM me
  8. arena_yang

    How to use the VHDL to design a PLL for CPLD?

    Please search DPLL,DLL,PLL in the forum
  9. arena_yang

    Simulation problem at Modelsim while simulating with Xilinx

    I think the license for Modelsim is not valid. I have also met the same thing
  10. arena_yang

    How to create the SDF & VHDL netlist for ModelSim SE 5.7

    sdf edf vhdl Typically, all the FPGA vendors' integrated development enviorement will all automatically generate a *.sdf file and a new *.vhd file which includes the specific FPGA device info and the time delay info etc. In ISE5.1/2i, it will generate a file like mydesign_timesim.vhd So if we...
  11. arena_yang

    IRQ controller design (in VHDL)

    My IRQ controller I remember that there is a post on irq controller on the web. Now I attach my design for ref. Any comments on it are valueable!!
  12. arena_yang

    Is the Xilinx ISE sw only a temp license?

    The Xilinx ISE needs Serial Number to install no license needed.
  13. arena_yang

    help: about using the Mentor Graphic's FPGA Advantage 5.4

    Hi friend, I had gotten some training on FPGA Advantage.but I have no the s/w at hand now, so I can't repeat the error you run in. But I think whether you could run/simulate your design in a Modelsim enviorment separately not invoke it in the HDL Designer.
  14. arena_yang

    i need help about timer counter.

    Very easy to implement it using FPGA or CPLD.
  15. arena_yang

    Why nobody has interest in DFT?

    I am interested in it,and I am studying it now.But I have no any more materials except the XAPP199(about writing an efficient TB). So I think if anybody is familiar with it,Please posts out your experience and special knowledge about it,Let's share! Thanks a lot! BTW:why I can't dnload the...
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