Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by Aravind_Selvaraj

  1. A

    What are some effective ways to create a self checking Testbench without ref model

    I am trying o create a TB for a certain digital design involving LUTs, Adders and memory blocks. The requirement here is to create self checking TB without a reference model so that it improves reusability and does not require changes in RM for every minor design change. Thanks in advance :)
  2. A

    Dual Clock Synchronization based Verilog Code

    Sorry for my language. The actual requirement is a trigger signal output which gives out a pulse whenever the posedges of the 2 clocks are very close (i.e. the both the edges occur in a time less than the duration of one period the higher clk (30Mhz)
  3. A

    Dual Clock Synchronization based Verilog Code

    There is an up counter whose clock is clk1(30Mhz). Since we already know that 120*30Mhz = 4uS or 250Khz(clk2). The output of the counter wcould be in phase with the actual clk2(signal). Could you suggest a method which triggers the output when either of clk2(250Khz) or counter output (again...
  4. A

    Dual Clock Synchronization based Verilog Code

    Synthesizable model is not required here. I am going to dump it in an FPGA and use it for the project. With respect to your I have one solution in mind. Please comment on it.
  5. A

    Dual Clock Synchronization based Verilog Code

    Hi everyone, I am designing an analog system which requires a Verilog code that performs the following. Inputs : clk1 (30Mhz) , clk2 (250Khz), reset ( So , the clk1 will complete 120cycles in the time clk2 completes one cycle) Output : delay[7:0] Problem : The output delay[7:0] should...
  6. A

    Dual Clock Synchronization Verilog code

    Hi everyone, I am designing an analog system which requires a Verilog code that performs the following. Inputs : clk1 (30Mhz) , clk2 (250Khz), reset ( So , the clk1 will complete 120cycles in the time clk2 completes one cycle) Output : delay[7:0] Problem : The output delay[7:0] should...
See more

Part and Inventory Search

Back
Top