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For soc chip power calculations one procedure is that use any power tool (ex: prime power) for calculation of power OR theritical method as follows. vendor will supply the power values for the MACROs , for memory macros we have comupte the power by using the following formula power P= (((read...
Re: The 10% IR drop we talk about represents VDD drop+VSS dr
IR drop is fall in VDD and rise VSS that means diference between fall in VDD and rise in VSS
EX : - 10%fall in VDD - 10%rise in VSS.
Re: Useful skew is operating condition sensitive?
in use-full skew method upsizing and downsizing of buffers or inserting buffer will be done, obously gate delays will varies according to pvt conditions, so skew will get effected.
Recovery time : -
minimum time that an asynchronous control input pin must be stable before the next active clock edge trasition.
Removal time: - minimum time that an asynchronous control input pin must be stable before being deasserted and after the prvious active...
Re: setup and hold time
we can check the setup and hold violation by using RTL code, if u have netlist by using tools loke ex:nc verilog we can find the setup and hold violations
when we analyze transistor level diagram for nand and nor, pmos trnasistor are in pararllel in the case nand, series in the case of nor for charging and discharging will be fast in the case for nand when u compare with nor.
when aggeresor is swithing and victim is in stable state then glitch will be geneted on victim net.
and noise will be generated beacause of the cross coupled capacitance of the nets the effect of nosie is glich.
synopsys lib file
generating .lib file is not easy. and we cannot generate .lib by using Astro, by using spice (h-spice from synopsys) simulation we can generate the .libs
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