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Recent content by ApTuPr

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    IP Testing-DFT

    Hello Folks I hope you guys are doing well. I was performing JTAG/Boundary Scan insertion & wrapping core. This is used for testing any IP. I am a bit confused about the flow of these. Which needs to be performed first whether JTAG -> Boundary Scan -> Wrapper design (or) different step...
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    Pad Cell

    Hello Folks I was performing Boundary-scan cell insertion but prior to that, I need to insert pad cells. But, while executing the command "preview_dft" in the design compiler. The following error comes (shows in the snapshot): I have tried to use the command:- set_bsd_linkage_port -port_list...
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    Pad Cells for boundary scan insertion

    Okay, I got it. Thank you so much wizard for your valuable time and help. I will now try by myself, if in case issue comes, will let you know. Hope you will help me out again. Thanks in advance
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    Pad Cells for boundary scan insertion

    Hey Wizard, Thank you for your help but the following are the doubts which need to be clarified: 1. How to know whether the particular pad is present in the library for boundary-scan or not? 2. Is there a different library for pad cell? 3. There are multiple pad cells in my library, how to...
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    Pad Cells for boundary scan insertion

    Hello Folks I am inserting boundary scan cells but in my design but before that, I need to insert pad cells for boundary-scan. How to know whether my library consists of pad cells or not? How to identify those pad cells in the library? Please help me out ASAP!!! Thanks in advance
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    DRC Rule for Well Tap cells

    Thanks a lot ThisIsNotSam. Will definitely look into it.
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    DRC Rule for Well Tap cells

    Thanks a ton dick_freebird for your info. Will definitely look into it and revert back if in case didn't understood anything.
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    DRC Rule for Well Tap cells

    Hello Folks What is the minimum cell interval for placing well tap and tie cells in Innovus? I need help ASAP!! :) Thanks in advance
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    Well Tap, End Cap and Filler cells.

    Hello Folks I am doing physical designing of ARM Core M0. I have two doubts: 1. Where to place special cells- End cap, well tap and Tie cells. May I know how and where to place them? Though I have theoretical idea but don't know after which step (floorplann, PnR, etc.) this should be done. 2...
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    [ARM] Implement ARM Core M0 as a testchip and verification using UVM

    Thanks so much dpaul. Will definitely look into it. Thanks for your help
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    [ARM] Implement ARM Core M0 as a testchip and verification using UVM

    Hi Folks, I hope you all are fine. I need your extensive help. I am going to work on a project to Implement ARM Core M0 as a test-chip and verify it using UVM. Can you please tell me how to initiate and the important resources I might need? Also, how to write its uvm code? Waiting for a reply...
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    [moved] CPU Usage error while doing netlist synthesis

    Hi dpaul Thank you so much for your response but I tried running same script on ARM core M3. It didn't gave this error. Core M3 RTL was much more complicated than this RTL. This M0 RTL is simpler than M3, still it is giving error.
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    [moved] CPU Usage error while doing netlist synthesis

    Hi Folks I have been doing RTL synthesis for given ARM Core M0. I have done synthesis in single Vt and now doing ECO in cadence tempus using Mix-Vt. But I am getting warning/error as shown in given picture. Could you please tell what is missing or exact problem occurring? Please tell me ASAP...
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    IR Drop analysis without .cir library

    Thank You so much timof. I will give it a try. If problem persists, will seek you help again :) Hope you won't mind.
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    IR Drop analysis without .cir library

    No, that I don't know. Can you please tell me the procedure?
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