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Recent content by anusha vasanta

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    how to read data available in nibble format

    hi all, i had nonce of 104 bits and header of 240 bits here i have to read these inputs but i had these values available in the format of nibbles when i was giving them it was showing error. how to read the nibbles even i had used %h still it was showing error. clear this doubt thanx in advance
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    how to identify the no.of clock cycles during simulation of design?

    Hi all, i had a very basic doubt as per the design i can understand the no.of clk cycles, but during my simulation how can i identify simply the no.of clock cycles my design is taking. any easy way help me thanx in advance..
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    writing the test bench in verilog

    Hi all, can anyone suggest me the best way of writing test bench for verifying all of the corner cases. you can put any link or some small gist regarding it. thanx in advance
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    asserting valid signals

    thankyou. but here both are asserted and deasserted during posedge of clk how the actual process is gng on internally.
  5. A

    asserting valid signals

    Hi all, is this a proper way of asserting and deasserting my valid signal. for (i=0;i< No_Patterns;i=i+1) begin //apply inputs @ (posedge clk) #Clk2Q data_valid_in = 1; //assert valid signals cipherkey_valid_in = 1; plain_text = data_input_vectors[i]...
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    [SOLVED] generate for loop inside a generate if loop

    thanks all, i am a new learner not a s/w hammer.thanks for all all of your suggestions.
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    [SOLVED] generate for loop inside a generate if loop

    thanku all for ur valuable guidance. 1.what my doubt is can we write a for loop inside a generate if condition? 2.if i had a code of multiple assign statements with in a generate block the result of first one is depending on 2nd assignment then how will be the order of execution take place. 3...
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    [SOLVED] generate for loop inside a generate if loop

    Hi all, can we use generate for loop inside a generate if loop which is outside of my always block, basically i want some instantiation using my for loop and here i had a register which i need to control using my if condition. that register will take a general value in my first for loop...
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    how to ctrl the operation of register

    can u suggest any good books which even had verilog-2001 constructs
  10. A

    what is the main essence of generate block and how is it useful??

    thanku then in how many clock cycles we can get the o/p for a generate block of above kind.
  11. A

    how to ctrl the operation of register

    HI everyone, i had a doubt help me, i had a tmp_reg of 128 bits in starting time that tmp_reg should contain a mic value of 128 bits , and from next onwards it should contain some other result, just like this it should run sequentially eg: tmp_reg= mic; gen block for(m=0;m<5;m=m+1) assign...
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    what is the main essence of generate block and how is it useful??

    genvar a; generate for(a=0;a<=7;a=a+1) //converting input data_in bits into bytes format begin : MEM assign data[a]= data_in [((a*8)+7):(a*8)]; end endgenerate hi all, here i had one generate which is converting my bits into bytes of 8...
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    instantiation with in an always block

    Haa i know that we can't use instantiation inside an always block but heard that gen block can be written inside always block so i got the doubt of that kind. Actually i had a tmp_reg contains one value and again i was assigning some other continous values to my tmp_reg like in the above...
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    instantiation with in an always block

    Hi all, is there any way to do the instantiation inside always block, here i had a code which had a tmp_reg first it should have one value and next it should take some other how could it be possible for this generate block genvar m; generate for(m=0;m<BLOCKS;m=m+1) begin :RAM4...
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    issues on data passage through wires

    hi all, i had a register of 30 bytes which is created by me from this reg i need to pass the data of 30 bytes to another module. for this i had taken 240 bits of wire, is it okay or entire 30 bytes can be passed through wire at a time. clear this doubt thanx in advance
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