Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hey
I have designed a median filter in FPGA using verilog. I have given the input in this programs using readmemh command in test bench. The problem is that For my input A,B,C,if i want to assign A=first value B=3rd value n C = 7th its giving xxxxx in output thus its unable to read unsequential...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
