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If there is a neg edge FF before a pos edge FF, the data read may be the older one or the updated data is lost. This is probable in multiple clock domain designs
to make sure this doesn't happen, we use lock up latches.
which tool are you going to use??
refer vlsi test principles and architectures text book. This book covers basics and takes you up the ladder one step at a time.
Apart from increasing abort limit and running full sequential options..I would like to suggest these additional things.
1. study the warnings fast scan reported during drc and check if you can get rid of them by doing some modifications.
2. If you have many black boxes in your design, the...
The basic difference between combinational and sequential ATPG is that, during sequential ATPG, one test vector may be insufficient to detect the target fault because the excitation and propagation conditions may necessitate some of the flip flop values to be specified at certain values.
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