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Recent content by Ansonng

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    HDMI Splitter by FPGA (HDMI Designer Pls Take A LOOK)

    fpga hdmi I am now trying to make a HDMI 1-8 splitter with a Xilinx Spartan 3A. This FPGA supports TMDS I/O standard. I think it is no problem to split TMDS Channel and Clock signals. However, I am getting puzzled to split other control signal listed below. 1. CEC - It is a bidirectional...
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    HDMI Data Rate Calculation Formula

    hdmi data rate mbits As HDMI 1.3 spec stated, it supports rate up to 340MHz (10.2 Gbps). I don't understand why 340MHz means 10.2 Gbps. I know HDMI has 3 data channels. Therefore, 340MHz x 3 = 1.02 Gbps why it is 10.2 Gbps
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    LCD Interface between CCIR656 and 8080 Bus with CPLD

    8080 lcd interface standard I mean the standard 8080 interface, not the MCU.
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    Need Datasheet of Driver IC NT7573

    nt7573 As subject stated. THX.
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    LCD Interface between CCIR656 and 8080 Bus with CPLD

    ccir656 interface Hi folks, We have a ASIC support CCIR656 LCD interface. Now I want to use a LCD with the 8080 Bus interface. I want to use a CPLD to implement the interface in-between. Is there any related source code can be provided? Thank you very much. BRs, ANSON
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    LCD for handheld device

    Hi, We are building a toy with a 2" LCD. I am not familiar with it. Anyone of you please help to answer my questions. 1. Any popular brand providing LCD for handheld device 2. The interface is stardardized or differnt LCD has different interface 3. How can I control the LCD? I need to...
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    Questions about using DDR2 for Spartan3E

    Using DDR2 for Spartan3E I plan to use a Spartan3E on my design and I want to have a DDR2 also. I read some document. SSTL18 class 2 is needed to interface DDR2. However, I found that Spartan3E only support SSTL18 class 1. Does it mean Spartan3E cannot support DDR2? What is the difference...
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    IDT71024S12TYG8 Compatible Part

    Is there any pin-to-pin compatible part to this IDT 128K x 8 CMOS Static RAM? Thank you.
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    Flash-based VS SRAM-based FPGA

    Hi, What is the pro and con between Flash-based VS SRAM-based FPGA? Thanks, Anson
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    Question about DC Biasing

    Here is the schematic. I want to bias the output part and set CM Vout = 0V
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    Question about DC Biasing

    I have a question for DC biasing. Suppose I have 4 MOS connecting like this. ___ Vpp | _| Vb4- o||_ mp1 | _| Vb3-o||_ mp2 |_Vout _| Vb2 -||_ mn2 | _| Vb1 -||_ mn1...
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    How HSpice Measure Differential Output

    acout=0 Hi all, I would like to to measure the differential output of my amp, and I tried the following way. vicm vicm vss 1350m vip vip vicm dc=0 ac=0.5 vin vicm vin dc=0 ac=0.5 .op .ac dec 2001 0.1 10G .probe vdb(von vop) vp(von vop) However, the value measured is always 0dB. Could...

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