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You are talking about an ideal case with zero-order hold pulse shaping at the output. Sure, no problem with that.
But if you look at the system practically, it ain't ideal. And here I am designing a chip that would be taped-out and used for an application. There are plenty of reasons at the...
The output of a DAC is not a time-discrete signal. It's analog in nature - a continuous-time, continuous amplitude signal. Hence, the FFT is not taken for no. of clock samples, instead for a value 100x times the clock samples.
That is because the spectrum of a signal is not limited to Fclock. The spectrum extends from -infinity to +infinity. That is where filters are used to reduce the spectrum to the bandwidth of interest and that is why aliasing and folding back of frequency components and noise takes place. MAybe...
Well. That is a very vague answer even to seek help. You should spend some time reading the fundamentals of Flash ADC design and set the target design specifications based on the application you want to target.
Fclock - 3Fin - is clearly an aliased tone. What I do not understand is how can aliasing increase the amplitude?
Performing FFT to Fclk/2 folds back the spectrum to Fclk/2. FFT beyond Fclk/2 shows the complete spectrum beyond Fclk/2 to which one can apply a filter that will give you the...
It would be better if you could support your arguement with examples, which of course is true.
What I meant is "generally", in majority of the applications Nyquist Sampling theorem is followed. Undersampling in data converters is not covered in the majority of universities at the fundamental...
I am simulating a DAC at 3GHz. The SFDR for different frequencies is as follows.
@ 100MHz = 67 dB
@ 700MHZ = 52 dB
@1.47GHz = 60 dB
I do not understand why the SFDR drops for middle frequencies. I have attached the graph for reference.
The Fclock - 3 * Fin amplitude is more than the 3 Fin. Why...
Thank you. for the replies.
I have added GND shielding on M5/M6. With that, the disturbances on the output reduced from 3mV to 250uV. I do not understand why there are disturbances (~900uV) in the R only extraction? It is also greater than in CC extraction (250uV). Is it the gate...
I am designing a 9 bit binary-weighted Nyquist DAC @3GHz. The schematics are ready with good results. I started the layout of the different blocks as Current Source Matrix, Current switches, Current switch drivers. I am not getting good results, mainly because of clock coupling to the...
1. You have to keep the devices as close as possible for good matching. You could try the Common Centroid layout.
2. If you are using fingers then look for threshold voltage variations. Check various parameters in schematic vs layout results.
By widening the Metal width, resistance decreases, and at the same time parasitic cap to the substrate increase. So maybe a medium width. But how to quantify it?
Do you have the answer to the question you posed?