Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by Ans5671

  1. A

    3GHz DAC SFDR

    You are talking about an ideal case with zero-order hold pulse shaping at the output. Sure, no problem with that. But if you look at the system practically, it ain't ideal. And here I am designing a chip that would be taped-out and used for an application. There are plenty of reasons at the...
  2. A

    3GHz DAC SFDR

    The output of a DAC is not a time-discrete signal. It's analog in nature - a continuous-time, continuous amplitude signal. Hence, the FFT is not taken for no. of clock samples, instead for a value 100x times the clock samples.
  3. A

    3GHz DAC SFDR

    That is because the spectrum of a signal is not limited to Fclock. The spectrum extends from -infinity to +infinity. That is where filters are used to reduce the spectrum to the bandwidth of interest and that is why aliasing and folding back of frequency components and noise takes place. MAybe...
  4. A

    Clock Frequency

    Well. That is a very vague answer even to seek help. You should spend some time reading the fundamentals of Flash ADC design and set the target design specifications based on the application you want to target.
  5. A

    3GHz DAC SFDR

    Fclock - 3Fin - is clearly an aliased tone. What I do not understand is how can aliasing increase the amplitude? Performing FFT to Fclk/2 folds back the spectrum to Fclk/2. FFT beyond Fclk/2 shows the complete spectrum beyond Fclk/2 to which one can apply a filter that will give you the...
  6. A

    Clock Frequency

    It would be better if you could support your arguement with examples, which of course is true. What I meant is "generally", in majority of the applications Nyquist Sampling theorem is followed. Undersampling in data converters is not covered in the majority of universities at the fundamental...
  7. A

    Clock Frequency

    Typically when they are used in A/D converters, Nyquist theorem is followed. Fin < Fs/2 to avoid aliasing of the input signal.
  8. A

    3GHz DAC SFDR

    I am simulating a DAC at 3GHz. The SFDR for different frequencies is as follows. @ 100MHz = 67 dB @ 700MHZ = 52 dB @1.47GHz = 60 dB I do not understand why the SFDR drops for middle frequencies. I have attached the graph for reference. The Fclock - 3 * Fin amplitude is more than the 3 Fin. Why...
  9. A

    Clock Frequency

    Yes. The 6 GHz refers to the sampling clock frequency in clocked comparators.
  10. A

    DAC Layout

    Thank you. for the replies. @guntherleet I have added GND shielding on M5/M6. With that, the disturbances on the output reduced from 3mV to 250uV. I do not understand why there are disturbances (~900uV) in the R only extraction? It is also greater than in CC extraction (250uV). Is it the gate...
  11. A

    DAC Layout

    Hello all, I am designing a 9 bit binary-weighted Nyquist DAC @3GHz. The schematics are ready with good results. I started the layout of the different blocks as Current Source Matrix, Current switches, Current switch drivers. I am not getting good results, mainly because of clock coupling to the...
  12. A

    Layout-dependent effect: tsmc 40nm CMOS problem

    1. You have to keep the devices as close as possible for good matching. You could try the Common Centroid layout. 2. If you are using fingers then look for threshold voltage variations. Check various parameters in schematic vs layout results.
  13. A

    Process Corner Simulations for D/A Converter.

    Is it important to do process corner simulations for a D/A converter.? Why /Why not? As I haven't come across PVT results in DAC papers.
  14. A

    RC circuit

    @timof By widening the Metal width, resistance decreases, and at the same time parasitic cap to the substrate increase. So maybe a medium width. But how to quantify it? Do you have the answer to the question you posed?

Part and Inventory Search

Top