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Hi, a couple of questions to understand the system better. You have mentioned that the circuit is differential so, is the input differential? and if its differential then wouldn't the feedback path need a differential DAC?
Also, after setting the N (better to choose power of 2's and long ~ 256 or 512), and the coprime integer M for input, Fin = M/N * Fclk.
The simulation needs to run for sufficient time.
Total sim time = initial time + N/Fclk.
Initial time is just to ignore some of the points in the beginning...
Hi, May I know what is by default 0.7um?
what is the size of the transistor to carry 3mA current?
I suppose you size the width of the transistor to carry 3mA of current and this would take care of the EM. The minimum sized transistors and its contact are designed to carry a maximum current...
I am trying to simulate the KT/C noise of a sample and hold. The Fs = 500MHz with a tracking time of 250ps.
How does the tracking time and sampling speed impact the noise.
What beat frequency do I need to choose in pss 500MHz or 2G(1/2*Tracking time)?
Also, the KT/C noise is not matching the...
@frankrose Thank you again for your response. The sampling stage is a Gate boosted switch followed by 80fF cap. and I need to drive this S&H with a 0.8V differential signal using 0.95V supply circuits. So, to design a fully differential unity gain circuit i would like to use an op amp.
But...
@sutapanaki
Thank you for your response. I would appreciate if you could back up your answer with a little explanation on how to determine the required op-amp bandwidth based on the ADC specs. I am trying to understand the design process as well. Why/why cannot I use a particular architecture.
Thank you for your response @frankrose . It's actually a SAR ADC with a 250ps sampling time. So, how do the parameters such as sampling time, Input frequency and resolution etc affect the op-amp specifications?
Hi, I am wanting to design an input buffer for a7 bit ADC with a sampling frequency of 2GSps. Max signal frequency = 40MHz. How to decide the specs of the op-amp (Av, input referred noise, settling time, Ugb, f3db, slew rate etc) to build a unity gain buffer.
Hi. I would like to design an input buffer to drive a 7bit ADC for 0.8Vppd input signal for up to 35MHz input at 0.9V supply. Can anyone suggest a suitable architecture? Thanks.
You are talking about an ideal case with zero-order hold pulse shaping at the output. Sure, no problem with that.
But if you look at the system practically, it ain't ideal. And here I am designing a chip that would be taped-out and used for an application. There are plenty of reasons at the...
The output of a DAC is not a time-discrete signal. It's analog in nature - a continuous-time, continuous amplitude signal. Hence, the FFT is not taken for no. of clock samples, instead for a value 100x times the clock samples.
That is because the spectrum of a signal is not limited to Fclock. The spectrum extends from -infinity to +infinity. That is where filters are used to reduce the spectrum to the bandwidth of interest and that is why aliasing and folding back of frequency components and noise takes place. MAybe...
Well. That is a very vague answer even to seek help. You should spend some time reading the fundamentals of Flash ADC design and set the target design specifications based on the application you want to target.
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