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I have a simple design (sort of hand-made multiplexer), let' s call it Self-MuX. I synthesized it with design compiler (synopsys) and them It is placed and route in IC compiler (synopsys). After that I am able to create its timing model (.lib/.db) with primetime, so in practice i can synthesize...
I am trying to create new cells made of standard cells in order to reuse them as a library in place&route . it is possible? which will be the correct steps?
thanks in advance
Nangate OpenSource Library developers answered me, that they provided the capacitance tables which is helpfully ... but they didn`t tell anything else.
thanks
I am using Nangate library with IC compiler (Synopsys). In order to perform a complete P&R , I need the tlu+ file (or its .itf file).
I know that the same info is provided at the capacitance tables for Cadence SoC Encounter (.capTbl) file. Does anyone how to translate .capTbl file into a .itf...
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