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Recent content by anne rachel

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    hysteresis loop in positive feedback latch circuit

    Hi, thanks for the reply. I have attached the pdf file which has discussed about the hysteresis in positive feedback latch circuit.. but I didn' t understand how they have come up with design specifications of the comparator with and without hysteresis...if possible,could u kindly help me out...
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    hysteresis loop in positive feedback latch circuit

    Hi everyone, Could anyone suggest me as to how to analyse the hysteresis loop of a positive feedback latch circuit? i need the small signal analysis of the circuit and the conditions to avoid hysteresis loop...if possible ,please post any material required for the same..thanks in advance ...
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    retaining of value of an integer in Verilog

    Hello all, I am unable to retain the value of the integer "result " . As soon as the first "always" block ends, the value of result is 0 as initialised but after the execution of the second "always" block, the correct value of "result" is being displayed. Can anyone help me in retaining the...
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    testing of 136 bit addition module written in verilog

    Hi all, I need help regarding the testing of 136 bit addition module which is written in Verilog language using Xilinx. Are there any testing tools available separately for testing this kind of huge bit string? Thanks in advance...
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    verilog:part select of register

    hello all, i have a reg [19:0]dummy, and i have a wire [ 7:0]dumvar, reg[3:0] ONES,TENS,HUNDREDS assign{HUNDREDS,TENS,ONES,dumvar}=dummy;(1) my algorithm is as follows: if either ONES or TENS or HUNDREDS is greater or equal to 5(0101), then i must add 0011(3) to the corresponding register i.e...
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    power analysis using xilinx power estimator

    $InjectFault system task is not supported in ISim simulator.Can anyone suggest me the simulators that support this system task?
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    power analysis using xilinx power estimator

    Hello all, I need some suggestions as to how to write a verilog code for stuck at 0 fault and analyse its power behavior using "Xilinx Power Estimator(XPE)... Thanks in advance :)
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    Inverter characteristics of FINFETS

    I was trying to simulate the inverter characteristics of FINFETS in HSpice.I am getting an inverted output of i(vin) instead of v(1) for a given input voltage Vin. Can anyone give me suggestions as to how to get the desired result? Following is the netlist for FINFETS inverter characteristics...
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    doubt regarding FINFET netlist in HSpice

    Thanks for the detailed explanation erikl :) But as far as i know,the syntax for the FINFETS connection line is as follows: Drain Gate_forward Gate_backward Source So, the two 1.2 V here correspond to Gate_forward and Gate_backward voltages since Finfet is double-gate MOS. - - - Updated - - -
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    doubt regarding FINFET netlist in HSpice

    Thanks a lot prestonee .. I am new to Spice . Sorry, if my doubt was silly. I have clearly understood now.
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    doubt regarding FINFET netlist in HSpice

    Thanks :) but my question is how does HSpice internally know that v3 is for gate to source voltage when the node "2" which is actually defined as gate in this netlist is not included while defining v3 voltage?Similarly, the drain node "1 " hasn't been mentioned anywhere in the statement that...
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    doubt regarding FINFET netlist in HSpice

    Hello everyone, Below is a netlist for implementation of drain characteristics of FINFET in HSpice. X1 1 2 2 0 DGNMOS1 v1 Vdd 0 2.5 v2 Vdd 1 0 v3 vcc 0 1.2 v4 vcc 2 0 .DC v1 0 2.5 .5 v3 0 1.2 .1 .trans 10u 10m .probe V(*) I(*) .end My doubt is if Vdd and vcc aren't defined anywhere...
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    Implementation of FINFETS in Hspice

    Can anyone give me a suggestion as to how to write a netlist for FINFETS in Hspice? I have searched but couldn't get a proper example for the same..I am quite new to FINFETS technology. Thanks in advance :)
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    reading values from file in verilog

    the code is quite big ..this is the piece of code which reads values from the file... module data_mem(index,A,B); input wire[0:2] index; output reg[0:128] A; output reg[0:128] B; reg [0:128] dmem[0:4]; initial $readmemb("data.txt", dmem); always @(index) begin A<=dmem[index]...
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    reading values from file in verilog

    I am not able to simulate a verilog code where i am reading the input values from a .txt file.Kindly help me in solving dis issue.... Thanks in advance....
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