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bgr measurements
please tell me how to measure bandgap accuracy in ppm??
and also what are range of ppm for a good bgr?
my output is varying from 1.176 to 1.22v and vref@25 is 1.198
1. how does bjt parameters (Ic,IE,IB,B,A) are effected by change in temperature?
2. do reverse saturation current depends on area of bjt cross section ?
Q> How does reference spurs and phase noise differentiates?
if i have reference spurs due to charge pump mismatches, wouldn't it
also results in jitter/phase noise?
How do we measure them experimentally?
Q> what are factors that contributes to fractional Spurs?
Q> how does charge pump current...
i am trying to understand memories , i may be completely wrong also.
please help me with your comments.
we use row and column decoders in memories.
if i have 128 * 128 bit memory ( to maintain aspect ratio)
i will have 14 bit address line.
as per my understanding i will give 7 bit of address...
what my understanding says:
in common mode as m3,m4 will act as diodes.
so gain of this stage will be lesser.
assume I1 current is in each branch of pair.
after keeping m6 and m7 some of current will be passed through m6,m7
current through m3,m4 will decrease so Gm of m3,m4 will decrease.
as...
your model card has resistor in form of subckt def
.subckt RFIFFP3 ....
grep this resitor name in model file , you will find it
now to instantiate subckt you have to start with X as that first letter of device name.
your prelayout netlist will have X in front
this problem occurs because of...
i feels that this is your design resistor and not parasitic.
i also expect that you will be having a resistor model with name "RDIFFP3" in your models.
do a trick:
your line 781 starts from rX7/X17/R2 as of now , make it XrX7/X17/R2
"add a X in front of that line" and try to run it.
if this...
Error:Nanosim:0x30201054:File "./netlist.sp", line 783, column 0, format SPICE: Can't locate resistor model
open file "netlist.sp" and go to line 783 ..
copy paste that line in forum...
i may be able to answer your problem....
even if we make two grounds digital and analog ,our substrate is still common to both..
so through substrates these grounds are connected ...
how does then two grounds benefits us ??
please correct me if i am wrong
as per my knowledge
nanosim doesn't have way t do multi threading or multi cpu.
nanosim is a fast spice. already they make internal matrix smaller and models equation to be shorter.
it will be overhead to further distribute this data on multiple cpus/cores
in terms of transistors,
if i say that i have node going from 0 to Z state.
in reality what will be voltage at that terminal ?
my understanding is that by putting node into tristate , i am switching off all paths of current from that node. so node should get remain in its original state...
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