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Recent content by anjf

  1. A

    Bochs IA-32 Emulator Project

    I use Simics. Simics provide many APIs and flexible interfaces.
  2. A

    mixed-language digital simulator usage

    Modelsim is much faster than Active HDL, especially when the post simulation with the .sdf file.
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    Synopsys Design Compiler FPGA (new tool)

    Re: Design Compiler FPGA I think the Fpga Compiler is better than Syplicity. The systhesi result of Fpga compiler is always faster. What is the reason of failure in the market?
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    Design Compiler: report_timing -delay min

    design compiler report_timing Is this command used to report the min hold time of the circuit? If so, according to the dc report, the min hold time=data required time in the report=clock uncertainty + output external delay + ... Why the output external delay is part of the min hold time?
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