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Recent content by anjali

  1. A

    assignment statement in Verilog

    delays can be used for modelling but synthesis tools ignore the delays.
  2. A

    standby leackage power reduction using Dual vth

    to reduce dynamic leakage power, we can use muti voltage cells.
  3. A

    clock multiplication by 2

    clock multipliers in verilog in general, we will not do clock multiplication at logic level. generally its not preffered. its better to use PLLs for that.
  4. A

    Difference between strobe-before-clock and strobe-after-clock test protocols

    can anybody please clarify the difference between strobe-before-clock and strobe-after-clock test protocols (in application perspective)
  5. A

    clock multiplication by 2

    clock multiplecation by 2 pass direct clock and delayed clock to an XOR gate. we can get multiply by 2 clk.
  6. A

    how to write into ram

    model the memory block. then write RTL to generate addr, data, control lines to that memory.
  7. A

    What do the terms fan-out and fan-in mean?

    fan out calculation for ttl by increasing output drive strength, we can increase the fan-out.
  8. A

    Verilog synthesis question

    both results same netlist with DC.
  9. A

    Users opinions on Magma tool

    Re: Magma - Suggestions perticularly for backend its really a good tool.
  10. A

    Using monopulse tracking system for X-band radar antenna ?

    Re: tracking system there lot of diff methods in monopulse tracking. i feel phase monopulse thech is advisable.
  11. A

    What do you need to cover in STA ?

    during STA, we need to check setup and hold, recovery and removal checks, DRCs, MAX/MIN path delays, etc..
  12. A

    Logic path delay for mux with enable line

    max operating freq = 1 / { max(path delay from ip to op, path delay from en to op) } for any circuit this is the way.
  13. A

    Synthesis Help:in verilog codes

    first, have a verilog code for multiplier with i/p & o/p ports. synthesize it. then have a top level environment which passes ips from the ips.txt ( can use $readmemb ) to the netlist.
  14. A

    Static Timing Analysis - Synopsys & Cadence

    many are using STA for timing analysis. its a powerfull tool.
  15. A

    Define the word BUFFER

    clock buffer - specifically used for clock network. - consumes more power than normal buffers
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