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learn verilog pdf
Verilog HDL: A guide to digital design and synthesis --by Samir Palnitkar
HDL chip design: A practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL and verilog ---by Douglas J Smith
Re: +ve Slack
It is always good to have positive slack rather than having zero slack. This is because in further process of chip design (like in backend) there may slight timing variations which can be accomodated if there is a positive slack.
Re: Always Block
The first one ,i.e.
always@(posedge clk)
The block under this executes at every postive edge of the clock
@posedge clk
This means that the block under this executes only once and that too, only at the first posedge of the clock
vhdl instance in verilog
Use mixed language simulators, for example synopsys has a tool by name VCS MX in which codes of both verilog and VHDL can be compiled and sumulated together (refer its pdfs for the commands)
Re: D Flip-Flop
D flip flop is the basic flop. It can be used as memories (which is used in many applications). It can also be used as dividers by just adding a not gate. Moreover other flops are not easy to use/modify as D flip flop
for loop verilog synthesis
It is synthesizable but it is always advised that for loops are not to be used in RTL coding. This is because it consumes lot of resources (like area etc.etc) . However u can use it in behavioral coding becuse we do not synthesize behavioral codes.
Hi,
it is better u do Mtech in VLSI and embedded systems from an accredited/recognised university.....this is beacuse it is easier to get a vlsi job if u are an Mtech rather than having 6 month certificate course
Setup time is critical for finding the max clock frequency
the setup time is the time interval before the active clock edge during which the data should remain unchanged
Hold time: Time interval after the active clock edge during which the data should remain unchanged
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